From 9b42e79dcffd981236902095b11c95aacbc402cc Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Wed, 27 Mar 2019 03:44:14 -0400 Subject: [PATCH] Added HW threads - Infinite loop --- rtl/VX_d_e_reg.v | 33 +- rtl/VX_decode.v | 97 +- rtl/VX_define.h | 3 + rtl/VX_define.v | 3 + rtl/VX_e_m_reg.v | 36 +- rtl/VX_execute.v | 117 +- rtl/VX_f_d_reg.v | 34 +- rtl/VX_fetch.v | 25 +- rtl/VX_forwarding.v | 47 +- rtl/VX_m_w_reg.v | 24 +- rtl/VX_memory.v | 33 +- rtl/VX_writeback.v | 19 +- rtl/Vortex.v | 736 ++++---- rtl/obj_dir/VVortex | Bin 360844 -> 377316 bytes rtl/obj_dir/VVortex.cpp | 2712 ++++++++++++++++++++--------- rtl/obj_dir/VVortex.h | 133 +- rtl/obj_dir/VVortex__ALL.a | Bin 39056 -> 55840 bytes rtl/obj_dir/VVortex__ALLcls.o | Bin 35868 -> 52608 bytes rtl/obj_dir/VVortex__verFiles.dat | 42 +- rtl/obj_dir/test_bench.o | Bin 63892 -> 64068 bytes rtl/results.txt | 414 ----- rtl/test_bench.h | 87 +- 22 files changed, 2756 insertions(+), 1839 deletions(-) diff --git a/rtl/VX_d_e_reg.v b/rtl/VX_d_e_reg.v index 52568c02..d8d168b3 100644 --- a/rtl/VX_d_e_reg.v +++ b/rtl/VX_d_e_reg.v @@ -7,7 +7,7 @@ module VX_d_e_reg ( input wire[4:0] in_rd, input wire[4:0] in_rs1, input wire[4:0] in_rs2, - input wire[31:0] in_reg_data[1:0], + input wire[31:0] in_reg_data[`NT_T2_M1:0], input wire[4:0] in_alu_op, input wire[1:0] in_wb, input wire in_rs2_src, // NEW @@ -26,7 +26,7 @@ module VX_d_e_reg ( input wire in_jal, input wire[31:0] in_jal_offset, input wire in_freeze, - input wire in_valid, + input wire[`NT_M1:0] in_valid, output wire[11:0] out_csr_address, // done output wire out_is_csr, // done @@ -34,7 +34,7 @@ module VX_d_e_reg ( output wire[4:0] out_rd, output wire[4:0] out_rs1, output wire[4:0] out_rs2, - output wire[31:0] out_reg_data[1:0], + output wire[31:0] out_reg_data[`NT_T2_M1:0], output wire[4:0] out_alu_op, output wire[1:0] out_wb, output wire out_rs2_src, // NEW @@ -47,14 +47,14 @@ module VX_d_e_reg ( output wire out_jal, output wire[31:0] out_jal_offset, output wire[31:0] out_PC_next, - output wire out_valid + output wire[`NT_M1:0] out_valid ); reg[4:0] rd; reg[4:0] rs1; reg[4:0] rs2; - reg[31:0] reg_data[1:0]; + reg[31:0] reg_data[`NT_T2_M1:0]; reg[4:0] alu_op; reg[1:0] wb; reg[31:0] PC_next_out; @@ -70,14 +70,22 @@ module VX_d_e_reg ( reg[31:0] curr_PC; reg jal; reg[31:0] jal_offset; - reg valid; + reg[`NT_M1:0] valid; + reg[31:0] reg_data_z[`NT_T2_M1:0]; + reg[`NT_M1:0] valid_z; + integer ini_reg; initial begin rd = 0; rs1 = 0; - reg_data[0] = 0; - reg_data[1] = 0; + for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1) + begin + reg_data[ini_reg] = 0; + reg_data_z[ini_reg] = 0; + valid[ini_reg] = 0; + valid_z[ini_reg] = 0; + end rs2 = 0; alu_op = 0; wb = `NO_WB; @@ -94,7 +102,6 @@ module VX_d_e_reg ( curr_PC = 0; jal = `NO_JUMP; jal_offset = 0; - valid = 0; end wire stalling; @@ -123,12 +130,6 @@ module VX_d_e_reg ( assign out_valid = valid; - - wire[31:0] reg_data_z[1:0]; - - assign reg_data_z[0] = 32'0; - assign reg_data_z[1] = 32'0; - always @(posedge clk) begin if (in_freeze == 1'h0) begin rd <= stalling ? 5'h0 : in_rd; @@ -150,7 +151,7 @@ module VX_d_e_reg ( jal <= stalling ? `NO_JUMP : in_jal; jal_offset <= stalling ? 32'h0 : in_jal_offset; curr_PC <= stalling ? 32'h0 : in_curr_PC; - valid <= stalling ? 1'b0 : in_valid; + valid <= stalling ? valid_z : in_valid; end end diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v index 93440281..3d2123cc 100644 --- a/rtl/VX_decode.v +++ b/rtl/VX_decode.v @@ -6,18 +6,18 @@ module VX_decode( input wire clk, input wire[31:0] in_instruction, input wire[31:0] in_curr_PC, - input wire in_valid, + input wire[`NT_M1:0] in_valid, // WriteBack inputs - input wire[31:0] in_write_data, + input wire[31:0] in_write_data[`NT_M1:0], input wire[4:0] in_rd, input wire[1:0] in_wb, - input wire in_wb_valid, + input wire[`NT_M1:0] in_wb_valid, // FORWARDING INPUTS input wire in_src1_fwd, - input wire[31:0] in_src1_fwd_data, + input wire[31:0] in_src1_fwd_data[`NT_M1:0], input wire in_src2_fwd, - input wire[31:0] in_src2_fwd_data, + input wire[31:0] in_src2_fwd_data[`NT_M1:0], output wire[11:0] out_csr_address, output wire out_is_csr, @@ -27,7 +27,7 @@ module VX_decode( output wire[4:0] out_rd, output wire[4:0] out_rs1, output wire[4:0] out_rs2, - output wire[31:0] out_reg_data[1:0], + output wire[31:0] out_reg_data[`NT_T2_M1:0], output wire[1:0] out_wb, output wire[4:0] out_alu_op, output wire out_rs2_src, @@ -40,14 +40,14 @@ module VX_decode( output reg[31:0] out_jal_offset, output reg[19:0] out_upper_immed, output wire[31:0] out_PC_next, - output wire out_valid + output wire[`NT_M1:0] out_valid ); wire[6:0] curr_opcode; - wire[31:0] rd1_register; - wire[31:0] rd2_register; + wire[31:0] rd1_register[`NT_M1:0]; + wire[31:0] rd2_register[`NT_M1:0]; wire is_itype; wire is_rtype; @@ -98,24 +98,56 @@ module VX_decode( reg[4:0] alu_op; reg[4:0] mul_alu; - wire[31:0] internal_rd1; - wire[31:0] internal_rd2; + // wire[31:0] internal_rd1; + // wire[31:0] internal_rd2; // always @(posedge clk) begin // $display("Decode: curr_pc: %h", in_curr_PC); // end - VX_register_file vx_register_file( - .clk(clk), - .in_valid(in_wb_valid), - .in_write_register(write_register), - .in_rd(in_rd), - .in_data(in_write_data), - .in_src1(out_rs1), - .in_src2(out_rs2), - .out_src1_data(rd1_register), - .out_src2_data(rd2_register) - ); + genvar index; + + generate + for (index=0; index < `NT; index=index+1) + begin: gen_code_label + VX_register_file vx_register_file( + .clk(clk), + .in_valid(in_wb_valid[index]), + .in_write_register(write_register), + .in_rd(in_rd), + .in_data(in_write_data[index]), + .in_src1(out_rs1), + .in_src2(out_rs2), + .out_src1_data(rd1_register[index]), + .out_src2_data(rd2_register[index]) + ); + end + endgenerate + + // VX_register_file vx_register_file_0( + // .clk(clk), + // .in_valid(in_wb_valid[0]), + // .in_write_register(write_register), + // .in_rd(in_rd), + // .in_data(in_write_data[1:0]), + // .in_src1(out_rs1), + // .in_src2(out_rs2), + // .out_src1_data(rd1_register), + // .out_src2_data(rd2_register) + // ); + + + // VX_register_file vx_register_file_1( + // .clk(clk), + // .in_valid(in_wb_valid), + // .in_write_register(write_register), + // .in_rd(in_rd), + // .in_data(in_write_data), + // .in_src1(out_rs1), + // .in_src2(out_rs2), + // .out_src1_data(rd1_register), + // .out_src2_data(rd2_register) + // ); assign out_valid = in_valid; @@ -151,13 +183,22 @@ module VX_decode( // ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction); - - assign internal_rd1 = ((is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register)); - assign internal_rd2 = (in_src2_fwd == 1'b1) ? in_src2_fwd_data : rd2_register; + genvar index_out_reg; + generate + for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) + begin + assign out_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg])); + assign out_reg_data[index_out_reg+1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg]; + end + endgenerate - assign out_reg_data[0] = internal_rd1; - assign out_reg_data[1] = internal_rd2; + // assign internal_rd1 = ((is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register)); + // assign internal_rd2 = (in_src2_fwd == 1'b1) ? in_src2_fwd_data : rd2_register; + + + // assign out_reg_data[0] = internal_rd1; + // assign out_reg_data[1] = internal_rd2; // always @(negedge clk) begin @@ -167,7 +208,7 @@ module VX_decode( // end assign out_is_csr = is_csr; - assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : internal_rd1; + assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : out_reg_data[0]; assign out_wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL : diff --git a/rtl/VX_define.h b/rtl/VX_define.h index c201bfa8..0ef8d8b6 100644 --- a/rtl/VX_define.h +++ b/rtl/VX_define.h @@ -1,5 +1,8 @@ +#define NT 2 +#define NT_M1 1 +#define NT_T2_M1 3 #define R_INST 51 #define L_INST 3 diff --git a/rtl/VX_define.v b/rtl/VX_define.v index b6ffe6a5..5bc5b8ce 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -1,4 +1,7 @@ +`define NT 2 +`define NT_M1 1 +`define NT_T2_M1 3 `define R_INST 7'd51 diff --git a/rtl/VX_e_m_reg.v b/rtl/VX_e_m_reg.v index 363cc2f8..696224f2 100644 --- a/rtl/VX_e_m_reg.v +++ b/rtl/VX_e_m_reg.v @@ -5,12 +5,12 @@ module VX_e_m_reg ( input wire clk, - input wire[31:0] in_alu_result, + input wire[31:0] in_alu_result[`NT_M1:0], input wire[4:0] in_rd, input wire[1:0] in_wb, input wire[4:0] in_rs1, input wire[4:0] in_rs2, - input wire[31:0] in_reg_data[1:0], + input wire[31:0] in_reg_data[`NT_T2_M1:0], input wire[2:0] in_mem_read, // NEW input wire[2:0] in_mem_write, // NEW input wire[31:0] in_PC_next, @@ -23,17 +23,17 @@ module VX_e_m_reg ( input wire in_jal, input wire[31:0] in_jal_dest, input wire in_freeze, - input wire in_valid, + input wire[`NT_M1:0] in_valid, output wire[11:0] out_csr_address, output wire out_is_csr, output wire[31:0] out_csr_result, - output wire[31:0] out_alu_result, + output wire[31:0] out_alu_result[`NT_M1:0], output wire[4:0] out_rd, output wire[1:0] out_wb, output wire[4:0] out_rs1, output wire[4:0] out_rs2, - output wire[31:0] out_reg_data[1:0], + output wire[31:0] out_reg_data[`NT_T2_M1:0], output wire[2:0] out_mem_read, output wire[2:0] out_mem_write, output wire[31:0] out_curr_PC, @@ -42,15 +42,15 @@ module VX_e_m_reg ( output wire out_jal, output wire[31:0] out_jal_dest, output wire[31:0] out_PC_next, - output wire out_valid + output wire[`NT_M1:0] out_valid ); - reg[31:0] alu_result; + reg[31:0] alu_result[`NT_M1:0]; reg[4:0] rd; reg[4:0] rs1; reg[4:0] rs2; - reg[31:0] reg_data[1:0]; + reg[31:0] reg_data[`NT_T2_M1:0]; reg[1:0] wb; reg[31:0] PC_next; reg[2:0] mem_read; @@ -63,16 +63,18 @@ module VX_e_m_reg ( reg[2:0] branch_type; reg jal; reg[31:0] jal_dest; - reg valid; + reg[`NT_M1:0] valid; + // reg[31:0] reg_data_z[`NT_T2_M1:0]; + // reg[`NT_M1:0] valid_z; + // reg[31:0] alu_result_z[`NT_M1:0]; + + integer ini_reg; initial begin - alu_result = 0; rd = 0; rs1 = 0; rs2 = 0; - reg_data[0] = 0; - reg_data[1] = 0; wb = 0; PC_next = 0; mem_read = `NO_MEM_READ; @@ -85,7 +87,15 @@ module VX_e_m_reg ( branch_type = 0; jal = `NO_JUMP; jal_dest = 0; - valid = 0; + for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1) + begin + reg_data[ini_reg] = 0; + // reg_data_z[ini_reg] = 0; + valid[ini_reg] = 0; + // valid_z[ini_reg] = 0; + // alu_result_z[ini_reg] = 0; + alu_result[ini_reg] = 0; + end end diff --git a/rtl/VX_execute.v b/rtl/VX_execute.v index 6e9625be..7e8dc4e3 100644 --- a/rtl/VX_execute.v +++ b/rtl/VX_execute.v @@ -2,59 +2,78 @@ `include "VX_define.v" module VX_execute ( - input wire[4:0] in_rd, - input wire[4:0] in_rs1, - input wire[4:0] in_rs2, - input wire[31:0] in_reg_data[1:0], - input wire[4:0] in_alu_op, - input wire[1:0] in_wb, - input wire in_rs2_src, // NEW - input wire[31:0] in_itype_immed, // new - input wire[2:0] in_mem_read, // NEW - input wire[2:0] in_mem_write, // NEW - input wire[31:0] in_PC_next, - input wire[2:0] in_branch_type, - input wire[19:0] in_upper_immed, - input wire[11:0] in_csr_address, // done - input wire in_is_csr, // done - input wire[31:0] in_csr_data, // done - input wire[31:0] in_csr_mask, // done - input wire in_jal, - input wire[31:0] in_jal_offset, - input wire[31:0] in_curr_PC, - input wire in_valid, + input wire[4:0] in_rd, + input wire[4:0] in_rs1, + input wire[4:0] in_rs2, + input wire[31:0] in_reg_data[`NT_T2_M1:0], + input wire[4:0] in_alu_op, + input wire[1:0] in_wb, + input wire in_rs2_src, // NEW + input wire[31:0] in_itype_immed, // new + input wire[2:0] in_mem_read, // NEW + input wire[2:0] in_mem_write, // NEW + input wire[31:0] in_PC_next, + input wire[2:0] in_branch_type, + input wire[19:0] in_upper_immed, + input wire[11:0] in_csr_address, // done + input wire in_is_csr, // done + input wire[31:0] in_csr_data, // done + input wire[31:0] in_csr_mask, // done + input wire in_jal, + input wire[31:0] in_jal_offset, + input wire[31:0] in_curr_PC, + input wire[`NT_M1:0] in_valid, - output wire[11:0] out_csr_address, - output wire out_is_csr, - output reg[31:0] out_csr_result, - output reg[31:0] out_alu_result, - output wire[4:0] out_rd, - output wire[1:0] out_wb, - output wire[4:0] out_rs1, - output wire[4:0] out_rs2, - output wire[31:0] out_reg_data[1:0], - output wire[2:0] out_mem_read, - output wire[2:0] out_mem_write, - output wire out_jal, - output wire[31:0] out_jal_dest, - output wire[31:0] out_branch_offset, - output wire out_branch_stall, - output wire[31:0] out_PC_next, - output wire out_valid + output wire[11:0] out_csr_address, + output wire out_is_csr, + output reg[31:0] out_csr_result, + output reg[31:0] out_alu_result[`NT_M1:0], + output wire[4:0] out_rd, + output wire[1:0] out_wb, + output wire[4:0] out_rs1, + output wire[4:0] out_rs2, + output wire[31:0] out_reg_data[`NT_T2_M1:0], + output wire[2:0] out_mem_read, + output wire[2:0] out_mem_write, + output wire out_jal, + output wire[31:0] out_jal_dest, + output wire[31:0] out_branch_offset, + output wire out_branch_stall, + output wire[31:0] out_PC_next, + output wire[`NT_M1:0] out_valid ); - VX_alu vx_alu( - .in_reg_data (in_reg_data), - .in_rs2_src (in_rs2_src), - .in_itype_immed(in_itype_immed), - .in_upper_immed(in_upper_immed), - .in_alu_op (in_alu_op), - .in_csr_data (in_csr_data), - .in_curr_PC (in_curr_PC), - .out_alu_result(out_alu_result) - ); + // VX_alu vx_alu( + // .in_reg_data (in_reg_data), + // .in_rs2_src (in_rs2_src), + // .in_itype_immed(in_itype_immed), + // .in_upper_immed(in_upper_immed), + // .in_alu_op (in_alu_op), + // .in_csr_data (in_csr_data), + // .in_curr_PC (in_curr_PC), + // .out_alu_result(out_alu_result) + // ); + + genvar index; + genvar index_2; + generate + for (index=0; index <= `NT; index=index+2) + begin: gen_code_label + assign index_2 = index / 2; + VX_alu vx_alu( + .in_reg_data (in_reg_data[index+1:index]), + .in_rs2_src (in_rs2_src), + .in_itype_immed(in_itype_immed), + .in_upper_immed(in_upper_immed), + .in_alu_op (in_alu_op), + .in_csr_data (in_csr_data), + .in_curr_PC (in_curr_PC), + .out_alu_result(out_alu_result[index_2]) + ); + end + endgenerate assign out_jal_dest = $signed(in_reg_data[0]) + $signed(in_jal_offset); @@ -66,7 +85,7 @@ module VX_execute ( `CSR_ALU_RW: out_csr_result = in_csr_mask; `CSR_ALU_RS: out_csr_result = in_csr_data | in_csr_mask; `CSR_ALU_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask); - default: out_csr_result = 32'hdeadbeef; + default: out_csr_result = 32'hdeadbeef; endcase end diff --git a/rtl/VX_f_d_reg.v b/rtl/VX_f_d_reg.v index 8585ce85..38705aa0 100644 --- a/rtl/VX_f_d_reg.v +++ b/rtl/VX_f_d_reg.v @@ -1,33 +1,37 @@ - +`include "VX_define.v" module VX_f_d_reg ( - input wire clk, - input wire reset, - input wire[31:0] in_instruction, - input wire in_valid, - input wire[31:0] in_curr_PC, - input wire in_fwd_stall, - input wire in_freeze, - output wire[31:0] out_instruction, - output wire[31:0] out_curr_PC, - output wire out_valid + input wire clk, + input wire reset, + input wire[31:0] in_instruction, + input wire[`NT_M1:0] in_valid, + input wire[31:0] in_curr_PC, + input wire in_fwd_stall, + input wire in_freeze, + output wire[31:0] out_instruction, + output wire[31:0] out_curr_PC, + output wire[`NT_M1:0] out_valid ); // always @(posedge clk) begin // $display("Fetch Inst: %d\tDecode Inst: %d", in_instruction, out_instruction); // end - reg[31:0] instruction; - reg[31:0] curr_PC; - reg valid; + reg[31:0] instruction; + reg[31:0] curr_PC; + reg[`NT_M1:0] valid; + + integer reset_cur_thread = 0; always @(posedge clk or posedge reset) begin if(reset) begin instruction <= 32'h0; curr_PC <= 32'h0; - valid <= 1'b0; + for (reset_cur_thread = 0; reset_cur_thread < `NT; reset_cur_thread = reset_cur_thread + 1) + valid[reset_cur_thread] <= 1'b0; + end else if (in_fwd_stall == 1'b1 || in_freeze == 1'b1) begin // $display("Because of FWD stall keeping pc: %h", curr_PC); end else begin diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index 7bfb0dcb..44151fee 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -1,4 +1,5 @@ +`include "VX_define.v" module VX_fetch ( input wire clk, @@ -15,10 +16,10 @@ module VX_fetch ( input wire in_debug, input wire[31:0] in_instruction, - output wire[31:0] out_instruction, - output wire out_delay, - output wire[31:0] out_curr_PC, - output wire out_valid + output wire[31:0] out_instruction, + output wire out_delay, + output wire[31:0] out_curr_PC, + output wire[`NT_M1:0] out_valid ); @@ -41,7 +42,17 @@ module VX_fetch ( reg[4:0] temp_state; reg[4:0] tempp_state; + reg[`NT_M1:0] valid; + + + // integer ini_cur_th = 0; + genvar out_cur_th; + initial begin + // for (ini_cur_th = 0; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1) + // valid[ini_cur_th] = 1; // Thread 1 active + valid[0] = 1; + valid[1] = 0; stall_reg = 0; delay_reg = 0; old = 0; @@ -89,7 +100,11 @@ module VX_fetch ( assign stall = in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || delay || in_freeze; assign out_instruction = stall ? 32'b0 : in_instruction; - assign out_valid = stall ? 1'b0 : 1'b1; + + generate + for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1) + assign out_valid[out_cur_th] = stall ? 1'b0 : valid[out_cur_th]; + endgenerate always @(*) begin diff --git a/rtl/VX_forwarding.v b/rtl/VX_forwarding.v index ff904645..b7db608c 100644 --- a/rtl/VX_forwarding.v +++ b/rtl/VX_forwarding.v @@ -10,7 +10,7 @@ module VX_forwarding ( // INFO FROM EXE input wire[4:0] in_execute_dest, input wire[1:0] in_execute_wb, - input wire[31:0] in_execute_alu_result, + input wire[31:0] in_execute_alu_result[`NT_M1:0], input wire[31:0] in_execute_PC_next, input wire in_execute_is_csr, input wire[11:0] in_execute_csr_address, @@ -18,8 +18,8 @@ module VX_forwarding ( // INFO FROM MEM input wire[4:0] in_memory_dest, input wire[1:0] in_memory_wb, - input wire[31:0] in_memory_alu_result, - input wire[31:0] in_memory_mem_data, + input wire[31:0] in_memory_alu_result[`NT_M1:0], + input wire[31:0] in_memory_mem_data[`NT_M1:0], input wire[31:0] in_memory_PC_next, input wire in_memory_is_csr, input wire[11:0] in_memory_csr_address, @@ -28,16 +28,16 @@ module VX_forwarding ( // INFO FROM WB input wire[4:0] in_writeback_dest, input wire[1:0] in_writeback_wb, - input wire[31:0] in_writeback_alu_result, - input wire[31:0] in_writeback_mem_data, + input wire[31:0] in_writeback_alu_result[`NT_M1:0], + input wire[31:0] in_writeback_mem_data[`NT_M1:0], input wire[31:0] in_writeback_PC_next, // OUT SIGNALS output wire out_src1_fwd, output wire out_src2_fwd, output wire out_csr_fwd, - output wire[31:0] out_src1_fwd_data, - output wire[31:0] out_src2_fwd_data, + output wire[31:0] out_src1_fwd_data[`NT_M1:0], + output wire[31:0] out_src2_fwd_data[`NT_M1:0], output wire[31:0] out_csr_fwd_data, output wire out_fwd_stall ); @@ -61,6 +61,21 @@ module VX_forwarding ( wire csr_exe_fwd; wire csr_mem_fwd; + wire[31:0] use_execute_PC_next[`NT_M1:0]; + wire[31:0] use_memory_PC_next[`NT_M1:0]; + wire[31:0] use_writeback_PC_next[`NT_M1:0]; + + + genvar index; + generate + for (index=0; index < `NT; index=index+1) + begin: gen_code_label + assign use_execute_PC_next[index] = in_execute_PC_next; + assign use_memory_PC_next[index] = in_memory_PC_next; + assign use_writeback_PC_next[index] = in_writeback_PC_next; + end + endgenerate + assign exe_mem_read = (in_execute_wb == `WB_MEM); assign mem_mem_read = (in_memory_wb == `WB_MEM); @@ -134,19 +149,19 @@ module VX_forwarding ( // if (out_fwd_stall) $display("FWD STALL"); // end - assign out_src1_fwd_data = src1_exe_fwd ? ((exe_jal) ? in_execute_PC_next : in_execute_alu_result) : - (src1_mem_fwd) ? ((mem_jal) ? in_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) : - ( src1_wb_fwd ) ? (wb_jal ? in_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) : - 32'hdeadbeef; // COMMENT + assign out_src1_fwd_data = src1_exe_fwd ? ((exe_jal) ? use_execute_PC_next : in_execute_alu_result) : + (src1_mem_fwd) ? ((mem_jal) ? use_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) : + ( src1_wb_fwd ) ? (wb_jal ? use_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) : + in_execute_alu_result; // last one should be deadbeef - assign out_src2_fwd_data = src2_exe_fwd ? ((exe_jal) ? in_execute_PC_next : in_execute_alu_result) : - (src2_mem_fwd) ? ((mem_jal) ? in_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) : - ( src2_wb_fwd ) ? (wb_jal ? in_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) : - 32'hdeadbeef; // COMMENT + assign out_src2_fwd_data = src2_exe_fwd ? ((exe_jal) ? use_execute_PC_next : in_execute_alu_result) : + (src2_mem_fwd) ? ((mem_jal) ? use_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) : + ( src2_wb_fwd ) ? (wb_jal ? use_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) : + in_execute_alu_result; // last one should be deadbeef assign out_csr_fwd_data = csr_exe_fwd ? in_execute_alu_result : csr_mem_fwd ? in_memory_csr_result : - 32'hdeadbeef; // COMMENT + in_execute_alu_result; // last one should be deadbeef diff --git a/rtl/VX_m_w_reg.v b/rtl/VX_m_w_reg.v index afadf59f..beca932b 100644 --- a/rtl/VX_m_w_reg.v +++ b/rtl/VX_m_w_reg.v @@ -4,47 +4,47 @@ module VX_m_w_reg ( input wire clk, - input wire[31:0] in_alu_result, - input wire[31:0] in_mem_result, // NEW + input wire[31:0] in_alu_result[`NT_M1:0], + input wire[31:0] in_mem_result[`NT_M1:0], // NEW input wire[4:0] in_rd, input wire[1:0] in_wb, input wire[4:0] in_rs1, input wire[4:0] in_rs2, input wire[31:0] in_PC_next, input wire in_freeze, - input wire in_valid, + input wire[`NT_M1:0] in_valid, - output wire[31:0] out_alu_result, - output wire[31:0] out_mem_result, // NEW + output wire[31:0] out_alu_result[`NT_M1:0], + output wire[31:0] out_mem_result[`NT_M1:0], // NEW output wire[4:0] out_rd, output wire[1:0] out_wb, output wire[4:0] out_rs1, output wire[4:0] out_rs2, output wire[31:0] out_PC_next, - output wire out_valid + output wire[`NT_M1:0] out_valid ); - reg[31:0] alu_result; - reg[31:0] mem_result; + reg[31:0] alu_result[`NT_M1:0]; + reg[31:0] mem_result[`NT_M1:0]; reg[4:0] rd; reg[4:0] rs1; reg[4:0] rs2; reg[1:0] wb; reg[31:0] PC_next; - reg valid; + reg[`NT_M1:0] valid; initial begin - alu_result = 0; - mem_result = 0; + // alu_result = 0; + // mem_result = 0; rd = 0; rs1 = 0; rs2 = 0; wb = 0; PC_next = 0; - valid = 0; + // valid = 0; end assign out_alu_result = alu_result; diff --git a/rtl/VX_memory.v b/rtl/VX_memory.v index c09e9049..06b07a22 100644 --- a/rtl/VX_memory.v +++ b/rtl/VX_memory.v @@ -3,23 +3,23 @@ module VX_memory ( - input wire[31:0] in_alu_result, + input wire[31:0] in_alu_result[`NT_M1:0], input wire[2:0] in_mem_read, input wire[2:0] in_mem_write, input wire[4:0] in_rd, input wire[1:0] in_wb, input wire[4:0] in_rs1, input wire[4:0] in_rs2, - input wire[31:0] in_rd2, + input wire[31:0] in_rd2[`NT_M1:0], input wire[31:0] in_PC_next, input wire[31:0] in_curr_PC, input wire[31:0] in_branch_offset, input wire[2:0] in_branch_type, - input wire in_valid, - input wire[31:0] in_cache_driver_out_data, + input wire[`NT_M1:0] in_valid, + input wire[31:0] in_cache_driver_out_data[`NT_M1:0], - output wire[31:0] out_alu_result, - output wire[31:0] out_mem_result, + output wire[31:0] out_alu_result[`NT_M1:0], + output wire[31:0] out_mem_result[`NT_M1:0], output wire[4:0] out_rd, output wire[1:0] out_wb, output wire[4:0] out_rs1, @@ -28,12 +28,12 @@ module VX_memory ( output wire[31:0] out_branch_dest, output wire out_delay, output wire[31:0] out_PC_next, - output wire out_valid, - output wire[31:0] out_cache_driver_in_address, + output wire[`NT_M1:0] out_valid, + output wire[31:0] out_cache_driver_in_address[`NT_M1:0], output wire[2:0] out_cache_driver_in_mem_read, output wire[2:0] out_cache_driver_in_mem_write, - output wire out_cache_driver_in_valid, - output wire[31:0] out_cache_driver_in_data + output wire[`NT_M1:0] out_cache_driver_in_valid, + output wire[31:0] out_cache_driver_in_data[`NT_M1:0] ); always @(in_mem_read, in_cache_driver_out_data) begin @@ -64,16 +64,15 @@ module VX_memory ( always @(*) begin case(in_branch_type) - `BEQ: out_branch_dir = (in_alu_result == 0) ? `TAKEN : `NOT_TAKEN; + `BEQ: out_branch_dir = (in_alu_result[0] == 0) ? `TAKEN : `NOT_TAKEN; `BNE: begin - out_branch_dir = (in_alu_result == 0) ? `NOT_TAKEN : `TAKEN; - // $display("Branch @%h is: %h", in_curr_PC, out_branch_dir); + out_branch_dir = (in_alu_result[0] == 0) ? `NOT_TAKEN : `TAKEN; end - `BLT: out_branch_dir = (in_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; - `BGT: out_branch_dir = (in_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; - `BLTU: out_branch_dir = (in_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; - `BGTU: out_branch_dir = (in_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; + `BLT: out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN; + `BGT: out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN; + `BLTU: out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN; + `BGTU: out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN; `NO_BRANCH: out_branch_dir = `NOT_TAKEN; default: out_branch_dir = `NOT_TAKEN; endcase // in_branch_type diff --git a/rtl/VX_writeback.v b/rtl/VX_writeback.v index 86f0bd4a..67687da4 100644 --- a/rtl/VX_writeback.v +++ b/rtl/VX_writeback.v @@ -3,13 +3,13 @@ module VX_writeback ( - input wire[31:0] in_alu_result, - input wire[31:0] in_mem_result, + input wire[31:0] in_alu_result[`NT_M1:0], + input wire[31:0] in_mem_result[`NT_M1:0], input wire[4:0] in_rd, input wire[1:0] in_wb, input wire[31:0] in_PC_next, - output wire[31:0] out_write_data, + output wire[31:0] out_write_data[`NT_M1:0], output wire[4:0] out_rd, output wire[1:0] out_wb ); @@ -24,10 +24,21 @@ module VX_writeback ( // end // end + wire[31:0] out_pc_data[`NT_M1:0]; + + + genvar index; + for (index=0; index < `NT; index=index+1) + assign out_pc_data[index] = in_PC_next; + generate + + + endgenerate + assign is_jal = in_wb == `WB_JAL; assign uses_alu = in_wb == `WB_ALU; - assign out_write_data = is_jal ? in_PC_next : + assign out_write_data = is_jal ? out_pc_data : uses_alu ? in_alu_result : in_mem_result; diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 297806c2..58fd66bb 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -1,15 +1,17 @@ +`include "VX_define.v" + module Vortex( - input wire clk, - input wire reset, - input wire[31:0] fe_instruction, - input wire[31:0] in_cache_driver_out_data, - output wire[31:0] curr_PC, - output wire[31:0] out_cache_driver_in_address, - output wire[2:0] out_cache_driver_in_mem_read, - output wire[2:0] out_cache_driver_in_mem_write, - output wire out_cache_driver_in_valid, - output wire[31:0] out_cache_driver_in_data + input wire clk, + input wire reset, + input wire[31:0] fe_instruction, + input wire[31:0] in_cache_driver_out_data[`NT_M1:0], + output wire[31:0] curr_PC, + output wire[31:0] out_cache_driver_in_address[`NT_M1:0], + output wire[2:0] out_cache_driver_in_mem_read, + output wire[2:0] out_cache_driver_in_mem_write, + output wire[`NT_M1:0] out_cache_driver_in_valid, + output wire[31:0] out_cache_driver_in_data[`NT_M1:0] ); @@ -19,128 +21,128 @@ assign curr_PC = fetch_curr_PC; wire[31:0] fetch_instruction; wire fetch_delay; wire[31:0] fetch_curr_PC; -wire fetch_valid; +wire[`NT_M1:0] fetch_valid; // From f_d_register wire[31:0] f_d_instruction; wire[31:0] f_d_curr_PC; -wire f_d_valid; +wire[`NT_M1:0] f_d_valid; // From decode -wire decode_branch_stall; -wire[11:0] decode_csr_address; -wire decode_is_csr; -wire[31:0] decode_csr_mask; -wire[4:0] decode_rd; -wire[4:0] decode_rs1; -wire[4:0] decode_rs2; -wire[31:0] decode_reg_data[1:0]; -wire[1:0] decode_wb; -wire[4:0] decode_alu_op; -wire decode_rs2_src; -reg[31:0] decode_itype_immed; -wire[2:0] decode_mem_read; -wire[2:0] decode_mem_write; -reg[2:0] decode_branch_type; -reg decode_jal; -reg[31:0] decode_jal_offset; -reg[19:0] decode_upper_immed; -wire[31:0] decode_PC_next; -wire decode_valid; +wire decode_branch_stall; +wire[11:0] decode_csr_address; +wire decode_is_csr; +wire[31:0] decode_csr_mask; +wire[4:0] decode_rd; +wire[4:0] decode_rs1; +wire[4:0] decode_rs2; +wire[31:0] decode_reg_data[`NT_T2_M1:0]; +wire[1:0] decode_wb; +wire[4:0] decode_alu_op; +wire decode_rs2_src; +reg[31:0] decode_itype_immed; +wire[2:0] decode_mem_read; +wire[2:0] decode_mem_write; +reg[2:0] decode_branch_type; +reg decode_jal; +reg[31:0] decode_jal_offset; +reg[19:0] decode_upper_immed; +wire[31:0] decode_PC_next; +wire[`NT_M1:0] decode_valid; // From d_e_register -wire[11:0] d_e_csr_address; -wire d_e_is_csr; -wire[31:0] d_e_csr_mask; -wire[4:0] d_e_rd; -wire[4:0] d_e_rs1; -wire[4:0] d_e_rs2; -wire[31:0] d_e_reg_data[1:0]; -wire[4:0] d_e_alu_op; -wire[1:0] d_e_wb; -wire d_e_rs2_src; -wire[31:0] d_e_itype_immed; -wire[2:0] d_e_mem_read; -wire[2:0] d_e_mem_write; -wire[2:0] d_e_branch_type; -wire[19:0] d_e_upper_immed; -wire[31:0] d_e_curr_PC; -wire d_e_jal; -wire[31:0] d_e_jal_offset; -wire[31:0] d_e_PC_next; -wire d_e_valid; +wire[11:0] d_e_csr_address; +wire d_e_is_csr; +wire[31:0] d_e_csr_mask; +wire[4:0] d_e_rd; +wire[4:0] d_e_rs1; +wire[4:0] d_e_rs2; +wire[31:0] d_e_reg_data[`NT_T2_M1:0]; +wire[4:0] d_e_alu_op; +wire[1:0] d_e_wb; +wire d_e_rs2_src; +wire[31:0] d_e_itype_immed; +wire[2:0] d_e_mem_read; +wire[2:0] d_e_mem_write; +wire[2:0] d_e_branch_type; +wire[19:0] d_e_upper_immed; +wire[31:0] d_e_curr_PC; +wire d_e_jal; +wire[31:0] d_e_jal_offset; +wire[31:0] d_e_PC_next; +wire[`NT_M1:0] d_e_valid; // From execute -wire execute_branch_stall; -wire[11:0] execute_csr_address; -wire execute_is_csr; -reg[31:0] execute_csr_result; -reg[31:0] execute_alu_result; -wire[4:0] execute_rd; -wire[1:0] execute_wb; -wire[4:0] execute_rs1; -wire[4:0] execute_rs2; -wire[31:0] execute_reg_data[1:0]; -wire[2:0] execute_mem_read; -wire[2:0] execute_mem_write; -wire execute_jal; -wire[31:0] execute_jal_dest; -wire[31:0] execute_branch_offset; -wire[31:0] execute_PC_next; -wire execute_valid; +wire execute_branch_stall; +wire[11:0] execute_csr_address; +wire execute_is_csr; +reg[31:0] execute_csr_result; +reg[31:0] execute_alu_result[`NT_M1:0]; +wire[4:0] execute_rd; +wire[1:0] execute_wb; +wire[4:0] execute_rs1; +wire[4:0] execute_rs2; +wire[31:0] execute_reg_data[`NT_T2_M1:0]; +wire[2:0] execute_mem_read; +wire[2:0] execute_mem_write; +wire execute_jal; +wire[31:0] execute_jal_dest; +wire[31:0] execute_branch_offset; +wire[31:0] execute_PC_next; +wire[`NT_M1:0] execute_valid; // From e_m_register -wire e_m_jal; -wire[31:0] e_m_jal_dest; -wire[11:0] e_m_csr_address; -wire e_m_is_csr; -wire[31:0] e_m_csr_result; -wire[31:0] e_m_alu_result; -wire[4:0] e_m_rd; -wire[1:0] e_m_wb; -wire[4:0] e_m_rs1; +wire e_m_jal; +wire[31:0] e_m_jal_dest; +wire[11:0] e_m_csr_address; +wire e_m_is_csr; +wire[31:0] e_m_csr_result; +wire[31:0] e_m_alu_result[`NT_M1:0]; +wire[4:0] e_m_rd; +wire[1:0] e_m_wb; +wire[4:0] e_m_rs1; /* verilator lint_off UNUSED */ -wire[31:0] e_m_reg_data[1:0]; +wire[31:0] e_m_reg_data[`NT_T2_M1:0]; /* verilator lint_on UNUSED */ -wire[4:0] e_m_rs2; -wire[2:0] e_m_mem_read; -wire[2:0] e_m_mem_write; -wire[31:0] e_m_curr_PC; -wire[31:0] e_m_branch_offset; -wire[2:0] e_m_branch_type; -wire[31:0] e_m_PC_next; -wire e_m_valid; +wire[4:0] e_m_rs2; +wire[2:0] e_m_mem_read; +wire[2:0] e_m_mem_write; +wire[31:0] e_m_curr_PC; +wire[31:0] e_m_branch_offset; +wire[2:0] e_m_branch_type; +wire[31:0] e_m_PC_next; +wire[`NT_M1:0] e_m_valid; // From memory -wire memory_delay; -wire memory_branch_dir; -wire[31:0] memory_branch_dest; -wire[31:0] memory_alu_result; -wire[31:0] memory_mem_result; -wire[4:0] memory_rd; -wire[1:0] memory_wb; -wire[4:0] memory_rs1; -wire[4:0] memory_rs2; -wire[31:0] memory_PC_next; -wire memory_valid; +wire memory_delay; +wire memory_branch_dir; +wire[31:0] memory_branch_dest; +wire[31:0] memory_alu_result[`NT_M1:0]; +wire[31:0] memory_mem_result[`NT_M1:0]; +wire[4:0] memory_rd; +wire[1:0] memory_wb; +wire[4:0] memory_rs1; +wire[4:0] memory_rs2; +wire[31:0] memory_PC_next; +wire[`NT_M1:0] memory_valid; // From m_w_register -wire[31:0] m_w_alu_result; -wire[31:0] m_w_mem_result; -wire[4:0] m_w_rd; -wire[1:0] m_w_wb; +wire[31:0] m_w_alu_result[`NT_M1:0]; +wire[31:0] m_w_mem_result[`NT_M1:0]; +wire[4:0] m_w_rd; +wire[1:0] m_w_wb; /* verilator lint_off UNUSED */ -wire[4:0] m_w_rs1; -wire[4:0] m_w_rs2; +wire[4:0] m_w_rs1; +wire[4:0] m_w_rs2; /* verilator lint_on UNUSED */ -wire[31:0] m_w_PC_next; -wire m_w_valid; +wire[31:0] m_w_PC_next; +wire[`NT_M1:0] m_w_valid; // From writeback -wire[31:0] writeback_write_data; +wire[31:0] writeback_write_data[`NT_M1:0]; wire[4:0] writeback_rd; wire[1:0] writeback_wb; @@ -156,8 +158,8 @@ wire forwarding_src2_fwd; wire forwarding_csr_fwd; wire[31:0] forwarding_csr_fwd_data; /* verilator lint_on UNUSED */ -wire[31:0] forwarding_src1_fwd_data; -wire[31:0] forwarding_src2_fwd_data; +wire[31:0] forwarding_src1_fwd_data[`NT_M1:0]; +wire[31:0] forwarding_src2_fwd_data[`NT_M1:0]; // Internal @@ -171,327 +173,331 @@ assign total_freeze = fetch_delay || memory_delay; VX_fetch vx_fetch( - .clk(clk), - .reset(reset), - .in_branch_dir(memory_branch_dir), - .in_freeze(total_freeze), - .in_branch_dest(memory_branch_dest), - .in_branch_stall(decode_branch_stall), - .in_fwd_stall(forwarding_fwd_stall), + .clk (clk), + .reset (reset), + .in_branch_dir (memory_branch_dir), + .in_freeze (total_freeze), + .in_branch_dest (memory_branch_dest), + .in_branch_stall (decode_branch_stall), + .in_fwd_stall (forwarding_fwd_stall), .in_branch_stall_exe(execute_branch_stall), - .in_jal(e_m_jal), - .in_jal_dest(e_m_jal_dest), - .in_interrupt(interrupt), - .in_debug(debug), - .in_instruction(fe_instruction), + .in_jal (e_m_jal), + .in_jal_dest (e_m_jal_dest), + .in_interrupt (interrupt), + .in_debug (debug), + .in_instruction (fe_instruction), - .out_instruction(fetch_instruction), - .out_delay(fetch_delay), - .out_curr_PC(fetch_curr_PC), - .out_valid(fetch_valid) + .out_instruction (fetch_instruction), + .out_delay (fetch_delay), + .out_curr_PC (fetch_curr_PC), + .out_valid (fetch_valid) ); VX_f_d_reg vx_f_d_reg( - .clk(clk), - .reset(reset), - .in_instruction(fetch_instruction), - .in_valid(fetch_valid), - .in_curr_PC(fetch_curr_PC), - .in_fwd_stall(forwarding_fwd_stall), - .in_freeze(total_freeze), + .clk (clk), + .reset (reset), + .in_instruction (fetch_instruction), + .in_valid (fetch_valid), + .in_curr_PC (fetch_curr_PC), + .in_fwd_stall (forwarding_fwd_stall), + .in_freeze (total_freeze), .out_instruction(f_d_instruction), - .out_curr_PC(f_d_curr_PC), - .out_valid(f_d_valid) + .out_curr_PC (f_d_curr_PC), + .out_valid (f_d_valid) ); VX_decode vx_decode( - .clk(clk), - .in_instruction(f_d_instruction), - .in_curr_PC(f_d_curr_PC), - .in_valid(f_d_valid), - .in_write_data(writeback_write_data), - .in_rd(writeback_rd), - .in_wb(writeback_wb), - .in_wb_valid(m_w_valid), - .in_src1_fwd(forwarding_src1_fwd), + .clk (clk), + .in_instruction (f_d_instruction), + .in_curr_PC (f_d_curr_PC), + .in_valid (f_d_valid), + .in_write_data (writeback_write_data), + .in_rd (writeback_rd), + .in_wb (writeback_wb), + .in_wb_valid (m_w_valid), + .in_src1_fwd (forwarding_src1_fwd), .in_src1_fwd_data(forwarding_src1_fwd_data), - .in_src2_fwd(forwarding_src2_fwd), + .in_src2_fwd (forwarding_src2_fwd), .in_src2_fwd_data(forwarding_src2_fwd_data), - .out_csr_address(decode_csr_address), - .out_is_csr(decode_is_csr), - .out_csr_mask(decode_csr_mask), + .out_csr_address (decode_csr_address), + .out_is_csr (decode_is_csr), + .out_csr_mask (decode_csr_mask), - .out_rd(decode_rd), - .out_rs1(decode_rs1), - .out_rs2(decode_rs2), - .out_reg_data(decode_reg_data), - .out_wb(decode_wb), - .out_alu_op(decode_alu_op), - .out_rs2_src(decode_rs2_src), - .out_itype_immed(decode_itype_immed), - .out_mem_read(decode_mem_read), - .out_mem_write(decode_mem_write), - .out_branch_type(decode_branch_type), + .out_rd (decode_rd), + .out_rs1 (decode_rs1), + .out_rs2 (decode_rs2), + .out_reg_data (decode_reg_data), + .out_wb (decode_wb), + .out_alu_op (decode_alu_op), + .out_rs2_src (decode_rs2_src), + .out_itype_immed (decode_itype_immed), + .out_mem_read (decode_mem_read), + .out_mem_write (decode_mem_write), + .out_branch_type (decode_branch_type), .out_branch_stall(decode_branch_stall), - .out_jal(decode_jal), - .out_jal_offset(decode_jal_offset), - .out_upper_immed(decode_upper_immed), - .out_PC_next(decode_PC_next), - .out_valid(decode_valid) + .out_jal (decode_jal), + .out_jal_offset (decode_jal_offset), + .out_upper_immed (decode_upper_immed), + .out_PC_next (decode_PC_next), + .out_valid (decode_valid) ); VX_d_e_reg vx_d_e_reg( - .clk(clk), - .in_rd(decode_rd), - .in_rs1(decode_rs1), - .in_rs2(decode_rs2), - .in_reg_data(decode_reg_data), - .in_alu_op(decode_alu_op), - .in_wb(decode_wb), - .in_rs2_src(decode_rs2_src), - .in_itype_immed(decode_itype_immed), - .in_mem_read(decode_mem_read), - .in_mem_write(decode_mem_write), - .in_PC_next(decode_PC_next), - .in_branch_type(decode_branch_type), - .in_fwd_stall(forwarding_fwd_stall), + .clk (clk), + .in_rd (decode_rd), + .in_rs1 (decode_rs1), + .in_rs2 (decode_rs2), + .in_reg_data (decode_reg_data), + .in_alu_op (decode_alu_op), + .in_wb (decode_wb), + .in_rs2_src (decode_rs2_src), + .in_itype_immed (decode_itype_immed), + .in_mem_read (decode_mem_read), + .in_mem_write (decode_mem_write), + .in_PC_next (decode_PC_next), + .in_branch_type (decode_branch_type), + .in_fwd_stall (forwarding_fwd_stall), .in_branch_stall(execute_branch_stall), - .in_upper_immed(decode_upper_immed), - .in_csr_address(decode_csr_address), - .in_is_csr(decode_is_csr), - .in_csr_mask(decode_csr_mask), - .in_curr_PC(f_d_curr_PC), - .in_jal(decode_jal), - .in_jal_offset(decode_jal_offset), - .in_freeze(total_freeze), - .in_valid(decode_valid), + .in_upper_immed (decode_upper_immed), + .in_csr_address (decode_csr_address), + .in_is_csr (decode_is_csr), + .in_csr_mask (decode_csr_mask), + .in_curr_PC (f_d_curr_PC), + .in_jal (decode_jal), + .in_jal_offset (decode_jal_offset), + .in_freeze (total_freeze), + .in_valid (decode_valid), .out_csr_address(d_e_csr_address), - .out_is_csr(d_e_is_csr), - .out_csr_mask(d_e_csr_mask), - .out_rd(d_e_rd), - .out_rs1(d_e_rs1), - .out_rs2(d_e_rs2), - .out_reg_data(d_e_reg_data), - .out_alu_op(d_e_alu_op), - .out_wb(d_e_wb), - .out_rs2_src(d_e_rs2_src), - .out_itype_immed(d_e_itype_immed), - .out_mem_read(d_e_mem_read), - .out_mem_write(d_e_mem_write), + .out_is_csr (d_e_is_csr), + .out_csr_mask (d_e_csr_mask), + .out_rd (d_e_rd), + .out_rs1 (d_e_rs1), + .out_rs2 (d_e_rs2), + .out_reg_data (d_e_reg_data), + .out_alu_op (d_e_alu_op), + .out_wb (d_e_wb), + .out_rs2_src (d_e_rs2_src), + .out_itype_immed(d_e_itype_immed), + .out_mem_read (d_e_mem_read), + .out_mem_write (d_e_mem_write), .out_branch_type(d_e_branch_type), .out_upper_immed(d_e_upper_immed), - .out_curr_PC(d_e_curr_PC), - .out_jal(d_e_jal), - .out_jal_offset(d_e_jal_offset), - .out_PC_next(d_e_PC_next), - .out_valid(d_e_valid) + .out_curr_PC (d_e_curr_PC), + .out_jal (d_e_jal), + .out_jal_offset (d_e_jal_offset), + .out_PC_next (d_e_PC_next), + .out_valid (d_e_valid) ); VX_execute vx_execute( - .in_rd(d_e_rd), - .in_rs1(d_e_rs1), - .in_rs2(d_e_rs2), - .in_reg_data(d_e_reg_data), - .in_alu_op(d_e_alu_op), - .in_wb(d_e_wb), - .in_rs2_src(d_e_rs2_src), - .in_itype_immed(d_e_itype_immed), - .in_mem_read(d_e_mem_read), - .in_mem_write(d_e_mem_write), - .in_PC_next(d_e_PC_next), - .in_branch_type(d_e_branch_type), - .in_upper_immed(d_e_upper_immed), - .in_csr_address(d_e_csr_address), - .in_is_csr(d_e_is_csr), - .in_csr_data(csr_decode_csr_data), - .in_csr_mask(d_e_csr_mask), - .in_jal(d_e_jal), - .in_jal_offset(d_e_jal_offset), - .in_curr_PC(d_e_curr_PC), - .in_valid(d_e_valid), + .in_rd (d_e_rd), + .in_rs1 (d_e_rs1), + .in_rs2 (d_e_rs2), + .in_reg_data (d_e_reg_data), + .in_alu_op (d_e_alu_op), + .in_wb (d_e_wb), + .in_rs2_src (d_e_rs2_src), + .in_itype_immed (d_e_itype_immed), + .in_mem_read (d_e_mem_read), + .in_mem_write (d_e_mem_write), + .in_PC_next (d_e_PC_next), + .in_branch_type (d_e_branch_type), + .in_upper_immed (d_e_upper_immed), + .in_csr_address (d_e_csr_address), + .in_is_csr (d_e_is_csr), + .in_csr_data (csr_decode_csr_data), + .in_csr_mask (d_e_csr_mask), + .in_jal (d_e_jal), + .in_jal_offset (d_e_jal_offset), + .in_curr_PC (d_e_curr_PC), + .in_valid (d_e_valid), - .out_csr_address(execute_csr_address), - .out_is_csr(execute_is_csr), - .out_csr_result(execute_csr_result), - .out_alu_result(execute_alu_result), - .out_rd(execute_rd), - .out_wb(execute_wb), - .out_rs1(execute_rs1), - .out_rs2(execute_rs2), - .out_reg_data(execute_reg_data), - .out_mem_read(execute_mem_read), - .out_mem_write(execute_mem_write), - .out_jal(execute_jal), - .out_jal_dest(execute_jal_dest), + .out_csr_address (execute_csr_address), + .out_is_csr (execute_is_csr), + .out_csr_result (execute_csr_result), + .out_alu_result (execute_alu_result), + .out_rd (execute_rd), + .out_wb (execute_wb), + .out_rs1 (execute_rs1), + .out_rs2 (execute_rs2), + .out_reg_data (execute_reg_data), + .out_mem_read (execute_mem_read), + .out_mem_write (execute_mem_write), + .out_jal (execute_jal), + .out_jal_dest (execute_jal_dest), .out_branch_offset(execute_branch_offset), - .out_branch_stall(execute_branch_stall), - .out_PC_next(execute_PC_next), - .out_valid(execute_valid) + .out_branch_stall (execute_branch_stall), + .out_PC_next (execute_PC_next), + .out_valid (execute_valid) ); - VX_e_m_reg vx_e_m_reg( - .clk(clk), - .in_alu_result(execute_alu_result), - .in_rd(execute_rd), - .in_wb(execute_wb), - .in_rs1(execute_rs1), - .in_rs2(execute_rs2), - .in_reg_data(execute_reg_data), - .in_mem_read(execute_mem_read), - .in_mem_write(execute_mem_write), - .in_PC_next(execute_PC_next), - .in_csr_address(execute_csr_address), - .in_is_csr(execute_is_csr), - .in_csr_result(execute_csr_result), - .in_curr_PC(d_e_curr_PC), - .in_branch_offset(execute_branch_offset), - .in_branch_type(d_e_branch_type), - .in_jal(execute_jal), - .in_jal_dest(execute_jal_dest), - .in_freeze(total_freeze), - .in_valid(execute_valid), + .clk (clk), + .in_alu_result (execute_alu_result), + .in_rd (execute_rd), + .in_wb (execute_wb), + .in_rs1 (execute_rs1), + .in_rs2 (execute_rs2), + .in_reg_data (execute_reg_data), + .in_mem_read (execute_mem_read), + .in_mem_write (execute_mem_write), + .in_PC_next (execute_PC_next), + .in_csr_address (execute_csr_address), + .in_is_csr (execute_is_csr), + .in_csr_result (execute_csr_result), + .in_curr_PC (d_e_curr_PC), + .in_branch_offset (execute_branch_offset), + .in_branch_type (d_e_branch_type), + .in_jal (execute_jal), + .in_jal_dest (execute_jal_dest), + .in_freeze (total_freeze), + .in_valid (execute_valid), - .out_csr_address(e_m_csr_address), - .out_is_csr(e_m_is_csr), - .out_csr_result(e_m_csr_result), - .out_alu_result(e_m_alu_result), - .out_rd(e_m_rd), - .out_wb(e_m_wb), - .out_rs1(e_m_rs1), - .out_rs2(e_m_rs2), - .out_reg_data(e_m_reg_data), - .out_mem_read(e_m_mem_read), - .out_mem_write(e_m_mem_write), - .out_curr_PC(e_m_curr_PC), + .out_csr_address (e_m_csr_address), + .out_is_csr (e_m_is_csr), + .out_csr_result (e_m_csr_result), + .out_alu_result (e_m_alu_result), + .out_rd (e_m_rd), + .out_wb (e_m_wb), + .out_rs1 (e_m_rs1), + .out_rs2 (e_m_rs2), + .out_reg_data (e_m_reg_data), + .out_mem_read (e_m_mem_read), + .out_mem_write (e_m_mem_write), + .out_curr_PC (e_m_curr_PC), .out_branch_offset(e_m_branch_offset), - .out_branch_type(e_m_branch_type), - .out_jal(e_m_jal), - .out_jal_dest(e_m_jal_dest), - .out_PC_next(e_m_PC_next), - .out_valid(e_m_valid) + .out_branch_type (e_m_branch_type), + .out_jal (e_m_jal), + .out_jal_dest (e_m_jal_dest), + .out_PC_next (e_m_PC_next), + .out_valid (e_m_valid) ); -VX_memory vx_memory( - .in_alu_result(e_m_alu_result), - .in_mem_read(e_m_mem_read), - .in_mem_write(e_m_mem_write), - .in_rd(e_m_rd), - .in_wb(e_m_wb), - .in_rs1(e_m_rs1), - .in_rs2(e_m_rs2), - .in_rd2(e_m_reg_data[1]), - .in_PC_next(e_m_PC_next), - .in_curr_PC(e_m_curr_PC), - .in_branch_offset(e_m_branch_offset), - .in_branch_type(e_m_branch_type), - .in_valid(e_m_valid), - .in_cache_driver_out_data(in_cache_driver_out_data), +wire[31:0] use_rd2[`NT_M1:0]; - .out_alu_result(memory_alu_result), - .out_mem_result(memory_mem_result), - .out_rd(memory_rd), - .out_wb(memory_wb), - .out_rs1(memory_rs1), - .out_rs2(memory_rs2), - .out_branch_dir(memory_branch_dir), - .out_branch_dest(memory_branch_dest), - .out_delay(memory_delay), - .out_PC_next(memory_PC_next), - .out_valid(memory_valid), - .out_cache_driver_in_address(out_cache_driver_in_address), - .out_cache_driver_in_mem_read(out_cache_driver_in_mem_read), +assign use_rd2[0] = e_m_reg_data[1]; +assign use_rd2[1] = e_m_reg_data[3]; + +VX_memory vx_memory( + .in_alu_result (e_m_alu_result), + .in_mem_read (e_m_mem_read), + .in_mem_write (e_m_mem_write), + .in_rd (e_m_rd), + .in_wb (e_m_wb), + .in_rs1 (e_m_rs1), + .in_rs2 (e_m_rs2), + .in_rd2 (use_rd2), + .in_PC_next (e_m_PC_next), + .in_curr_PC (e_m_curr_PC), + .in_branch_offset (e_m_branch_offset), + .in_branch_type (e_m_branch_type), + .in_valid (e_m_valid), + .in_cache_driver_out_data (in_cache_driver_out_data), + + .out_alu_result (memory_alu_result), + .out_mem_result (memory_mem_result), + .out_rd (memory_rd), + .out_wb (memory_wb), + .out_rs1 (memory_rs1), + .out_rs2 (memory_rs2), + .out_branch_dir (memory_branch_dir), + .out_branch_dest (memory_branch_dest), + .out_delay (memory_delay), + .out_PC_next (memory_PC_next), + .out_valid (memory_valid), + .out_cache_driver_in_address (out_cache_driver_in_address), + .out_cache_driver_in_mem_read (out_cache_driver_in_mem_read), .out_cache_driver_in_mem_write(out_cache_driver_in_mem_write), - .out_cache_driver_in_data(out_cache_driver_in_data), - .out_cache_driver_in_valid(out_cache_driver_in_valid) + .out_cache_driver_in_data (out_cache_driver_in_data), + .out_cache_driver_in_valid (out_cache_driver_in_valid) ); VX_m_w_reg vx_m_w_reg( - .clk(clk), - .in_alu_result(memory_alu_result), - .in_mem_result(memory_mem_result), - .in_rd(memory_rd), - .in_wb(memory_wb), - .in_rs1(memory_rs1), - .in_rs2(memory_rs2), - .in_PC_next(memory_PC_next), - .in_freeze(total_freeze), - .in_valid(memory_valid), + .clk (clk), + .in_alu_result (memory_alu_result), + .in_mem_result (memory_mem_result), + .in_rd (memory_rd), + .in_wb (memory_wb), + .in_rs1 (memory_rs1), + .in_rs2 (memory_rs2), + .in_PC_next (memory_PC_next), + .in_freeze (total_freeze), + .in_valid (memory_valid), .out_alu_result(m_w_alu_result), .out_mem_result(m_w_mem_result), - .out_rd(m_w_rd), - .out_wb(m_w_wb), - .out_rs1(m_w_rs1), - .out_rs2(m_w_rs2), - .out_PC_next(m_w_PC_next), - .out_valid(m_w_valid) + .out_rd (m_w_rd), + .out_wb (m_w_wb), + .out_rs1 (m_w_rs1), + .out_rs2 (m_w_rs2), + .out_PC_next (m_w_PC_next), + .out_valid (m_w_valid) ); VX_writeback vx_writeback( - .in_alu_result(m_w_alu_result), - .in_mem_result(m_w_mem_result), - .in_rd(m_w_rd), - .in_wb(m_w_wb), - .in_PC_next(m_w_PC_next), + .in_alu_result (m_w_alu_result), + .in_mem_result (m_w_mem_result), + .in_rd (m_w_rd), + .in_wb (m_w_wb), + .in_PC_next (m_w_PC_next), .out_write_data(writeback_write_data), - .out_rd(writeback_rd), - .out_wb(writeback_wb) + .out_rd (writeback_rd), + .out_wb (writeback_wb) ); VX_forwarding vx_forwarding( - .in_decode_src1(decode_rs1), - .in_decode_src2(decode_rs2), - .in_decode_csr_address(decode_csr_address), + .in_decode_src1 (decode_rs1), + .in_decode_src2 (decode_rs2), + .in_decode_csr_address (decode_csr_address), - .in_execute_dest(execute_rd), - .in_execute_wb(execute_wb), - .in_execute_alu_result(execute_alu_result), - .in_execute_PC_next(execute_PC_next), - .in_execute_is_csr(execute_is_csr), - .in_execute_csr_address(execute_csr_address), + .in_execute_dest (execute_rd), + .in_execute_wb (execute_wb), + .in_execute_alu_result (execute_alu_result), + .in_execute_PC_next (execute_PC_next), + .in_execute_is_csr (execute_is_csr), + .in_execute_csr_address (execute_csr_address), - .in_memory_dest(memory_rd), - .in_memory_wb(memory_wb), - .in_memory_alu_result(memory_alu_result), - .in_memory_mem_data(memory_mem_result), - .in_memory_PC_next(memory_PC_next), - .in_memory_is_csr(e_m_is_csr), - .in_memory_csr_address(e_m_csr_address), - .in_memory_csr_result(e_m_csr_result), + .in_memory_dest (memory_rd), + .in_memory_wb (memory_wb), + .in_memory_alu_result (memory_alu_result), + .in_memory_mem_data (memory_mem_result), + .in_memory_PC_next (memory_PC_next), + .in_memory_is_csr (e_m_is_csr), + .in_memory_csr_address (e_m_csr_address), + .in_memory_csr_result (e_m_csr_result), - .in_writeback_dest(m_w_rd), - .in_writeback_wb(m_w_wb), + .in_writeback_dest (m_w_rd), + .in_writeback_wb (m_w_wb), .in_writeback_alu_result(m_w_alu_result), - .in_writeback_mem_data(m_w_mem_result), - .in_writeback_PC_next(m_w_PC_next), + .in_writeback_mem_data (m_w_mem_result), + .in_writeback_PC_next (m_w_PC_next), - .out_src1_fwd(forwarding_src1_fwd), - .out_src2_fwd(forwarding_src2_fwd), - .out_csr_fwd(forwarding_csr_fwd), - .out_src1_fwd_data(forwarding_src1_fwd_data), - .out_src2_fwd_data(forwarding_src2_fwd_data), - .out_csr_fwd_data(forwarding_csr_fwd_data), - .out_fwd_stall(forwarding_fwd_stall) + .out_src1_fwd (forwarding_src1_fwd), + .out_src2_fwd (forwarding_src2_fwd), + .out_csr_fwd (forwarding_csr_fwd), + .out_src1_fwd_data (forwarding_src1_fwd_data), + .out_src2_fwd_data (forwarding_src2_fwd_data), + .out_csr_fwd_data (forwarding_csr_fwd_data), + .out_fwd_stall (forwarding_fwd_stall) ); VX_csr_handler vx_csr_handler( - .clk(clk), + .clk (clk), .in_decode_csr_address(decode_csr_address), - .in_mem_csr_address(e_m_csr_address), - .in_mem_is_csr(e_m_is_csr), - .in_mem_csr_result(e_m_csr_result), - .in_wb_valid(m_w_valid), + .in_mem_csr_address (e_m_csr_address), + .in_mem_is_csr (e_m_is_csr), + .in_mem_csr_result (e_m_csr_result), + .in_wb_valid (m_w_valid[0]), - .out_decode_csr_data(csr_decode_csr_data) + .out_decode_csr_data (csr_decode_csr_data) ); diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex index d5d4f191aa27158489e058f995d8cd85867fe96e..c756b2295c76fe88d818b97c2e27b6092c0c19e2 100755 GIT binary patch delta 77497 zcmZr(2S5}@7rvRfQ!EHdkzN!98=``OihzQi1;yB~*C^IlV?|IPa-OH?s6*7m5{()g z2654dVgq6{Vo4-M6O3&!nxL^@<$p7~$8q_S|L1n*&3oS~(`SpTQk?IlG|Vv6-=@`A z{kLuHruOx->@*q#PFO)3;Rwe~3Uz`))C56ZD?~D|ueorHPAOdvg$iCN zcI7T`V>MZ-=r&rLM3|}eDp9kI4zo~;RI2?p`i+H}Q9~h@Y@=_0x?91uQF#+~(_Y#L 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zo|J*7XW;S-yf6)8s^d*#2vL=RAIiYptZhS_^SWUjS!~1g9xl8hiU_Vol%1 z@JHeL)n?Ti=Day;9PY>CI@j7&>}=X?0&cIwbrmj{`-wKV+Ty|zpvcG79v5B_#Uxxa zt)0W1gR*YL?QOX57YM_h&(B2Xv@Fr7 zz|(MDkLwm(x8u447v_M1#;m(={r{>!A^cfYJiBqraA&B2RdS8fWo@45Txwl733t=4 papqaICpinOXRpDr3bLcO%!$tWmPH;X&tbR`=M$D*S4-B5_&>#aKQjOT diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp index 955fcce1..aa0c793d 100644 --- a/rtl/obj_dir/VVortex.cpp +++ b/rtl/obj_dir/VVortex.cpp @@ -95,28 +95,28 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp) VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__1\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_fetch.v:129 - vlTOPp->Vortex__DOT__vx_fetch__DOT__stall_reg = - ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)); - // ALWAYS at VX_fetch.v:129 + // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__old = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC); - // ALWAYS at VX_fetch.v:129 + // ALWAYS at VX_fetch.v:144 + vlTOPp->Vortex__DOT__vx_fetch__DOT__stall_reg = + ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)); + // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__BR_reg = ((IData)(vlTOPp->reset) ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__memory_branch_dest)); - // ALWAYS at VX_fetch.v:129 + // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg = 0U; - // ALWAYS at VX_fetch.v:129 + // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__real_PC = ((IData)(vlTOPp->reset) ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use)); - // ALWAYS at VX_fetch.v:129 + // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__state = ((IData)(vlTOPp->reset) ? 0U : @@ -129,15 +129,15 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp) ((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) ? 2U : 0U)))); - // ALWAYS at VX_fetch.v:129 + // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__JAL_reg = ((IData)(vlTOPp->reset) ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest)); - // ALWAYS at VX_fetch.v:129 + // ALWAYS at VX_fetch.v:144 vlTOPp->Vortex__DOT__vx_fetch__DOT__prev_debug = 0U; - // ALWAYS at VX_fetch.v:71 + // ALWAYS at VX_fetch.v:82 vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg) ? vlTOPp->Vortex__DOT__vx_fetch__DOT__old @@ -165,33 +165,61 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Variables // Begin mtask footprint all: - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0,4,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,0,0); VL_SIG8(__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0,0,0); VL_SIG16(__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0); VL_SIG16(__Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0); - VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0,31,0); VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v2,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1,31,0); // Body + __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 = 0U; __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 0U; - __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0 = 0U; - // ALWAYS at VX_e_m_reg.v:113 + // ALWAYS at VX_e_m_reg.v:123 __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0 = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data - [1U]; + [3U]; __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data + [2U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v2 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v3 = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data [0U]; - // ALWAYS at VX_csr_handler.v:34 - vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address - = vlTOPp->Vortex__DOT__decode_csr_address; - // ALWAYS at VX_csr_handler.v:34 - vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle - = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle); - // ALWAYS at VX_d_e_reg.v:132 + // ALWAYS at VX_m_w_reg.v:60 + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result + [1U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result + [0U]; + // ALWAYS at VX_m_w_reg.v:60 + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result + [1U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result + [0U]; + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed = (0xfffffU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : ((0x37U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) @@ -204,37 +232,75 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU) : 0U)))); - // ALWAYS at VX_d_e_reg.v:132 + // ALWAYS at VX_csr_handler.v:34 + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address + = vlTOPp->Vortex__DOT__decode_csr_address; + // ALWAYS at VX_csr_handler.v:34 + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle + = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle); + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src = (1U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (1U & (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype) | (0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) ? 1U : 0U)))); - // ALWAYS at VX_e_m_reg.v:113 + // ALWAYS at VX_e_m_reg.v:123 + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result + [0U]; + // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed; - // ALWAYS at VX_csr_handler.v:34 - if (vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid) { - vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret - = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret); - } - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write; - // ALWAYS at VX_e_m_reg.v:113 + // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read; - // ALWAYS at VX_e_m_reg.v:113 + // ALWAYS at VX_e_m_reg.v:123 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write; + // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal; - // ALWAYS at VX_e_m_reg.v:113 + // ALWAYS at VX_e_m_reg.v:123 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC; + // ALWAYS at VX_e_m_reg.v:123 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest = (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset); + // ALWAYS at VX_csr_handler.v:34 + if ((1U & (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid))) { + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret + = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret); + } + // ALWAYS at VX_register_file.v:36 + if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & ((IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid) + >> 1U))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } + // ALWAYS at VX_register_file.v:36 + if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } // ALWAYS at VX_csr_handler.v:43 if (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr) { __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0 @@ -243,87 +309,124 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) __Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address; } - // ALWAYS at VX_register_file.v:36 - if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) - & (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid))) { - __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0 - = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next - : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result - : vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result)); - __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0 = 1U; - __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0 - = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; - } - // ALWAYS at VX_d_e_reg.v:132 + // ALWAYS at VX_d_e_reg.v:133 __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data + [3U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data + [2U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data [1U]); - __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1 + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data [0U]); - // ALWAYSPOST at VX_e_m_reg.v:123 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[1U] + // ALWAYSPOST at VX_e_m_reg.v:133 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[3U] = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[2U] = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v2; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v3; + // ALWAYSPOST at VX_m_w_reg.v:62 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[1U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[0U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1; + // ALWAYSPOST at VX_m_w_reg.v:63 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[1U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[0U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1; + // ALWAYSPOST at VX_e_m_reg.v:125 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1; + // ALWAYSPOST at VX_register_file.v:39 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0; + } + // ALWAYSPOST at VX_register_file.v:39 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0; + } // ALWAYSPOST at VX_csr_handler.v:45 if (__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0) { vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr[__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0] = __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0; } - // ALWAYSPOST at VX_register_file.v:39 - if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0) { - vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0] - = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0; - } - // ALWAYSPOST at VX_d_e_reg.v:137 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[1U] + // ALWAYSPOST at VX_d_e_reg.v:138 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[3U] = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[2U] = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data + [2U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[1U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data [0U]; - // ALWAYS at VX_d_e_reg.v:132 + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [0U]; + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_branch_type)); - // ALWAYS at VX_d_e_reg.v:132 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = - ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? 0U : vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC); - vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC - + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset - << 1U)); - // ALWAYS at VX_d_e_reg.v:132 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed - = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed); - vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; - // ALWAYS at VX_d_e_reg.v:132 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write - = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? 7U : ((0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) - ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xcU) : 7U))); vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; - // ALWAYS at VX_d_e_reg.v:132 + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 7U : ((3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU) : 7U))); - // ALWAYS at VX_d_e_reg.v:132 + vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; + // ALWAYS at VX_d_e_reg.v:133 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write + = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 7U : ((0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU) : 7U))); + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal = ((~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) & ((0x6fU == @@ -347,7 +450,28 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) (0xfffU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)))))))); - // ALWAYS at VX_d_e_reg.v:132 + // ALWAYS at VX_d_e_reg.v:133 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = + ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC); + vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset + << 1U)); + // ALWAYS at VX_d_e_reg.v:133 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed); + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + // ALWAYS at VX_e_m_reg.v:123 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) @@ -379,12 +503,18 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) >> 0x14U)))) ? 0xb0000000U : 0xdeadbeefU) : 0xdeadbeefU)))); - // ALWAYS at VX_e_m_reg.v:113 + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; + // ALWAYS at VX_m_w_reg.v:60 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; + // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address; - // ALWAYS at VX_e_m_reg.v:113 + // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__is_csr; - // ALWAYS at VX_e_m_reg.v:113 + // ALWAYS at VX_e_m_reg.v:123 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_result = ((0xdU == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask @@ -395,30 +525,38 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ? (vlTOPp->Vortex__DOT__csr_decode_csr_data & ((IData)(0xffffffffU) - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask)) : 0xdeadbeefU))); - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result - = vlTOPp->in_cache_driver_out_data; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result - = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; - // ALWAYS at VX_m_w_reg.v:60 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + [2U]; vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[1U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[0U] = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data [0U]; + vlTOPp->Vortex__DOT__e_m_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data + [3U]; + vlTOPp->Vortex__DOT__e_m_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data + [2U]; vlTOPp->Vortex__DOT__e_m_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data [1U]; vlTOPp->Vortex__DOT__e_m_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data [0U]; + vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [1U]; + vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [0U]; + vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [0U]; vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle) @@ -441,32 +579,73 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) : vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr [vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address])))); + vlTOPp->Vortex__DOT__d_e_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + [3U]; + vlTOPp->Vortex__DOT__d_e_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + [2U]; vlTOPp->Vortex__DOT__d_e_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data [1U]; vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data [0U]; - vlTOPp->out_cache_driver_in_data = vlTOPp->Vortex__DOT__e_m_reg_data + vlTOPp->Vortex__DOT__use_rd2[0U] = vlTOPp->Vortex__DOT__e_m_reg_data [1U]; + vlTOPp->Vortex__DOT__use_rd2[1U] = vlTOPp->Vortex__DOT__e_m_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] + = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] + = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] + = vlTOPp->Vortex__DOT__e_m_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] + = vlTOPp->Vortex__DOT__e_m_alu_result[0U]; vlTOPp->Vortex__DOT__execute_branch_stall = ((0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal)); - // ALWAYS at VX_d_e_reg.v:132 + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + // ALWAYS at VX_d_e_reg.v:133 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC)); + // ALWAYS at VX_e_m_reg.v:123 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; + // ALWAYS at VX_e_m_reg.v:123 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; + // ALWAYS at VX_e_m_reg.v:123 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid; + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_csr_address)); - // ALWAYS at VX_d_e_reg.v:132 + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__is_csr = ((~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)); - // ALWAYS at VX_d_e_reg.v:132 + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xeU)) ? (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)) - : vlTOPp->Vortex__DOT__vx_decode__DOT__internal_rd1)); - // ALWAYS at VX_d_e_reg.v:132 + : vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + [0U])); + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0xfU : (((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction @@ -474,34 +653,38 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) ? (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu) : (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu))); - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result - = vlTOPp->Vortex__DOT__execute_alu_result; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; - // ALWAYS at VX_e_m_reg.v:113 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[3U] + = vlTOPp->Vortex__DOT__d_e_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2U] + = vlTOPp->Vortex__DOT__d_e_reg_data[2U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] = vlTOPp->Vortex__DOT__d_e_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] = vlTOPp->Vortex__DOT__d_e_reg_data[0U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] + = vlTOPp->Vortex__DOT__use_rd2[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] + = vlTOPp->Vortex__DOT__use_rd2[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [1U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [1U])); + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[0U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [0U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [0U])); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [1U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data - [0U]; - vlTOPp->out_cache_driver_in_address = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; // ALWAYS at VX_memory.v:65 vlTOPp->Vortex__DOT__memory_branch_dir = (1U & ((4U @@ -512,17 +695,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ? ((~ (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) & (~ - (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] >> 0x1fU))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) ? - (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] >> 0x1fU) : (~ - (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] >> 0x1fU)))) : ( (2U @@ -531,32 +717,82 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ((1U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) ? - (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] >> 0x1fU) : (0U - != vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result)) + != + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U])) : ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) & (0U - == vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result))))); - vlTOPp->out_cache_driver_in_valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; - // ALWAYS at VX_d_e_reg.v:132 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = ( - (~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) - & (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid)); - // ALWAYS at VX_d_e_reg.v:132 - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out - = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) - ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC)); - // ALWAYS at VX_d_e_reg.v:132 + == + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]))))); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [0U]; + vlTOPp->Vortex__DOT__writeback_write_data[1U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [1U]; + vlTOPp->Vortex__DOT__writeback_write_data[0U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [0U]; + vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [1U]; + vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [0U]; + vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = (0x1fU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 7U))); - // ALWAYS at VX_d_e_reg.v:132 + // ALWAYS at VX_d_e_reg.v:133 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) ? 0U : @@ -601,243 +837,393 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)) ? 1U : 0U)))); + vlTOPp->out_cache_driver_in_valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; + // ALWAYS at VX_d_e_reg.v:133 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z) + : (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid)); + vlTOPp->Vortex__DOT__execute_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data + [3U]; + vlTOPp->Vortex__DOT__execute_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data + [2U]; vlTOPp->Vortex__DOT__execute_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data [1U]; vlTOPp->Vortex__DOT__execute_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2 + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed - : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data + : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data [1U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [1U]); + vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [1U]; + vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] + = vlTOPp->Vortex__DOT__writeback_write_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] + = vlTOPp->Vortex__DOT__writeback_write_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] + = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] + = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[3U] + = vlTOPp->Vortex__DOT__execute_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2U] + = vlTOPp->Vortex__DOT__execute_reg_data[2U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[1U] = vlTOPp->Vortex__DOT__execute_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[0U] = vlTOPp->Vortex__DOT__execute_reg_data[0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__mult_signed_result + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data [0U]), - VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)); + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)); // ALWAYS at VX_alu.v:47 - vlTOPp->Vortex__DOT__execute_alu_result = ((0x10U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? ( - (8U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? 0U - : - ((4U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((0U - == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - : - VL_MODDIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)) - : - ((0U - == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - : - VL_MODDIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((0U - == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 0xffffffffU - : - VL_DIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)) - : - ((0U - == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 0xffffffffU - : - VL_DIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)))) - : - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? (IData)( - (((QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U])) - * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - >> 0x20U)) - : (IData)( - (((((QData)((IData)( - VL_NEGATE_I((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( (1U - & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data + & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data [0U] >> 0x1fU)))))) - << 0x20U) - | (QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U]))) - * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - >> 0x20U))) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? (IData)( - (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__mult_signed_result - >> 0x20U)) - : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__mult_signed_result))))) - : ( - (8U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((4U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? vlTOPp->Vortex__DOT__csr_decode_csr_data - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? vlTOPp->Vortex__DOT__csr_decode_csr_data - : - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC - + - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed - << 0xcU)))) - : - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed - << 0xcU) - : - ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 0U - : 0xffffffffU)) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2 - & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U]) - : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)))) - : - ((4U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - VL_SHIFTRS_III(32,32,5, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], - (0x1fU - & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)) - : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - >> - (0x1fU - & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - : - ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 1U - : 0U))) - : - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (VL_LTS_III(1,32,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 1U - : 0U) - : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - << - (0x1fU - & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)))))); + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U]) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:47 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U]) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))))); + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] + = vlTOPp->Vortex__DOT__execute_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] + = vlTOPp->Vortex__DOT__execute_alu_result[0U]; } -VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__3\n"); ); +VL_INLINE_OPT void VVortex::_combo__TOP__3(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__3\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_register_file.v:43 - vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register - = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers - [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0x14U))]; - // ALWAYS at VX_register_file.v:43 - vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register - = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers - [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU))]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] + = vlTOPp->in_cache_driver_out_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] + = vlTOPp->in_cache_driver_out_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [0U]; + vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [1U]; + vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] + = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] + = vlTOPp->Vortex__DOT__memory_mem_result[0U]; } void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_settle__TOP__4\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[0U] = 0U; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1U] = 0U; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] + = vlTOPp->in_cache_driver_out_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] + = vlTOPp->in_cache_driver_out_data[0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [0U]; vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype = ((0x13U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) | (3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))); @@ -856,7 +1242,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:316 + // ALWAYS at VX_decode.v:357 vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)); vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = @@ -882,7 +1268,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)))); - // ALWAYS at VX_decode.v:266 + // ALWAYS at VX_decode.v:307 vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U == (0x7fU @@ -913,7 +1299,21 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { ? 2U : 1U))) : 0U); - // ALWAYS at VX_decode.v:255 + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [0U]; + vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [1U]; + vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [0U]; + // ALWAYS at VX_decode.v:296 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -1129,13 +1529,79 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { >> 0x19U))) ? 0U : 1U)))))))))); + vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [1U]; + vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] + = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] + = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] + = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] + = vlTOPp->Vortex__DOT__memory_mem_result[0U]; } -void VVortex::_initial__TOP__5(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_initial__TOP__5\n"); ); +VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__5\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // INITIAL at VX_fetch.v:44 + // ALWAYS at VX_register_file.v:43 + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file.v:43 + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file.v:43 + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file.v:43 + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data; +} + +void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_initial__TOP__6\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // INITIAL at VX_fetch.v:51 + vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (1U + | (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)); + vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (1U + & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)); vlTOPp->Vortex__DOT__vx_fetch__DOT__stall_reg = 0U; vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg = 0U; vlTOPp->Vortex__DOT__vx_fetch__DOT__old = 0U; @@ -1145,21 +1611,15 @@ void VVortex::_initial__TOP__5(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_fetch__DOT__BR_reg = 0U; vlTOPp->Vortex__DOT__vx_fetch__DOT__prev_debug = 0U; // INITIAL at VX_m_w_reg.v:39 - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result = 0U; - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result = 0U; vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = 0U; vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = 0U; vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = 0U; - vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid = 0U; // INITIAL at VX_csr_handler.v:27 vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle = VL_ULL(0); vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret = VL_ULL(0); vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address = 0U; - // INITIAL at VX_e_m_reg.v:69 - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result = 0U; + // INITIAL at VX_e_m_reg.v:74 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = 0U; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] = 0U; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[1U] = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read = 7U; @@ -1172,11 +1632,28 @@ void VVortex::_initial__TOP__5(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = 0U; vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest = 0U; - vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = 0U; - // INITIAL at VX_d_e_reg.v:76 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = (2U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid)); + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = (1U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid)); + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] = 0U; + // INITIAL at VX_d_e_reg.v:79 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = (2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid)); + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z = + (2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z)); vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = (1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid)); + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z = + (1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z)); vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = 0U; @@ -1192,23 +1669,13 @@ void VVortex::_initial__TOP__5(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal = 0U; vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset = 0U; - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = 0U; } -VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__6\n"); ); +VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__7\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_f_d_reg.v:26 - if (vlTOPp->reset) { - vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)))) { - vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid - = (1U & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall))); - } - } - // ALWAYS at VX_f_d_reg.v:26 + // ALWAYS at VX_f_d_reg.v:28 if (vlTOPp->reset) { vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC = 0U; } else { @@ -1217,7 +1684,19 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC; } } - // ALWAYS at VX_f_d_reg.v:26 + // ALWAYS at VX_f_d_reg.v:28 + if (vlTOPp->reset) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + = (2U & (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid)); + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + = (1U & (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid)); + } else { + if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)))) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + = vlTOPp->Vortex__DOT__fetch_valid; + } + } + // ALWAYS at VX_f_d_reg.v:28 if (vlTOPp->reset) { vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction = 0U; } else { @@ -1227,7 +1706,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) ? 0U : vlTOPp->fe_instruction); } } - // ALWAYS at VX_fetch.v:95 + // ALWAYS at VX_fetch.v:110 vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = ( ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg))) @@ -1256,7 +1735,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:316 + // ALWAYS at VX_decode.v:357 vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)); vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = @@ -1282,7 +1761,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xcU)))); - // ALWAYS at VX_decode.v:266 + // ALWAYS at VX_decode.v:307 vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U == (0x7fU @@ -1323,7 +1802,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); - // ALWAYS at VX_decode.v:255 + // ALWAYS at VX_decode.v:296 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -1576,6 +2055,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); + vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)); vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling = ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); @@ -1594,13 +2076,23 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))) | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); + vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); + vlTOPp->Vortex__DOT__fetch_valid = ((2U & (IData)(vlTOPp->Vortex__DOT__fetch_valid)) + | (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)))); + vlTOPp->Vortex__DOT__fetch_valid = ((1U & (IData)(vlTOPp->Vortex__DOT__fetch_valid)) + | (2U & (((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + << 1U) + & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)))); } -void VVortex::_settle__TOP__7(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_settle__TOP__7\n"); ); +void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_settle__TOP__8\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_fetch.v:71 + // ALWAYS at VX_fetch.v:82 vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg) ? vlTOPp->Vortex__DOT__vx_fetch__DOT__old @@ -1621,6 +2113,14 @@ void VVortex::_settle__TOP__7(VVortex__Syms* __restrict vlSymsp) { : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__state)) ? vlTOPp->Vortex__DOT__vx_fetch__DOT__JAL_reg : vlTOPp->Vortex__DOT__vx_fetch__DOT__real_PC))))))); + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle) @@ -1648,61 +2148,36 @@ void VVortex::_settle__TOP__7(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset << 1U)); + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data + [2U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[1U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data [1U]; vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[0U] = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data [0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [0U]; vlTOPp->out_cache_driver_in_valid = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid; - vlTOPp->out_cache_driver_in_address = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; - // ALWAYS at VX_memory.v:65 - vlTOPp->Vortex__DOT__memory_branch_dir = (1U & - ((4U - & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) - ? ( - (2U - & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) - ? - ((~ (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) - & (~ - (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result - >> 0x1fU))) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) - ? - (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result - >> 0x1fU) - : - (~ - (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result - >> 0x1fU)))) - : ( - (2U - & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) - ? - (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result - >> 0x1fU) - : - (0U - != vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result)) - : - ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) - & (0U - == vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result))))); vlTOPp->Vortex__DOT__execute_branch_stall = ((0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal)); - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data - [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data - [0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd = ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) @@ -1713,23 +2188,43 @@ void VVortex::_settle__TOP__7(VVortex__Syms* __restrict vlSymsp) { >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [1U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [1U])); + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[0U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [0U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [0U])); + vlTOPp->Vortex__DOT__e_m_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data + [3U]; + vlTOPp->Vortex__DOT__e_m_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data + [2U]; vlTOPp->Vortex__DOT__e_m_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data [1U]; vlTOPp->Vortex__DOT__e_m_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data [0U]; - // ALWAYS at VX_fetch.v:95 - vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = ( - ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg))) - ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest - : - (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg))) - ? vlTOPp->Vortex__DOT__memory_branch_dest - : vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use)); - vlTOPp->Vortex__DOT__d_e_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result [1U]; - vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result [0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction @@ -1744,13 +2239,28 @@ void VVortex::_settle__TOP__7(VVortex__Syms* __restrict vlSymsp) { & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))); - vlTOPp->out_cache_driver_in_data = vlTOPp->Vortex__DOT__e_m_reg_data + vlTOPp->Vortex__DOT__d_e_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + [3U]; + vlTOPp->Vortex__DOT__d_e_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + [2U]; + vlTOPp->Vortex__DOT__d_e_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data [1U]; - vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] - = vlTOPp->Vortex__DOT__d_e_reg_data[1U]; - vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] - = vlTOPp->Vortex__DOT__d_e_reg_data[0U]; + vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data + [0U]; + vlTOPp->Vortex__DOT__writeback_write_data[1U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [1U]; + vlTOPp->Vortex__DOT__writeback_write_data[0U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [0U]; + vlTOPp->Vortex__DOT__use_rd2[0U] = vlTOPp->Vortex__DOT__e_m_reg_data + [1U]; + vlTOPp->Vortex__DOT__use_rd2[1U] = vlTOPp->Vortex__DOT__e_m_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] + = vlTOPp->Vortex__DOT__e_m_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] + = vlTOPp->Vortex__DOT__e_m_alu_result[0U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) @@ -1775,18 +2285,85 @@ void VVortex::_settle__TOP__7(VVortex__Syms* __restrict vlSymsp) { != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[3U] + = vlTOPp->Vortex__DOT__d_e_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2U] + = vlTOPp->Vortex__DOT__d_e_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] + = vlTOPp->Vortex__DOT__writeback_write_data [1U]; - vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] + = vlTOPp->Vortex__DOT__writeback_write_data [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data[1U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] + = vlTOPp->Vortex__DOT__use_rd2[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] + = vlTOPp->Vortex__DOT__use_rd2[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [1U]; - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data[0U] - = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result [0U]; + // ALWAYS at VX_memory.v:65 + vlTOPp->Vortex__DOT__memory_branch_dir = (1U & + ((4U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? ( + (2U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + ((~ (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + & (~ + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU) + : + (~ + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU)))) + : ( + (2U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU) + : + (0U + != + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U])) + : + ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) + & (0U + == + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]))))); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)); vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling = ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); @@ -1805,329 +2382,737 @@ void VVortex::_settle__TOP__7(VVortex__Syms* __restrict vlSymsp) { & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))) | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); + vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [0U]; + vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [1U]; + vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [0U]; + // ALWAYS at VX_fetch.v:110 + vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = ( + ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : + (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use)); + vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__fetch_valid = ((2U & (IData)(vlTOPp->Vortex__DOT__fetch_valid)) + | (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)))); + vlTOPp->Vortex__DOT__fetch_valid = ((1U & (IData)(vlTOPp->Vortex__DOT__fetch_valid)) + | (2U & (((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) + << 1U) + & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)))); + vlTOPp->Vortex__DOT__execute_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data + [3U]; + vlTOPp->Vortex__DOT__execute_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data + [2U]; vlTOPp->Vortex__DOT__execute_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data [1U]; vlTOPp->Vortex__DOT__execute_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data [0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2 + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed - : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data + : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data [1U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [1U]); + vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [1U]; + vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [0U]; + vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] + = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] + = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[3U] + = vlTOPp->Vortex__DOT__execute_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2U] + = vlTOPp->Vortex__DOT__execute_reg_data[2U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[1U] = vlTOPp->Vortex__DOT__execute_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[0U] = vlTOPp->Vortex__DOT__execute_reg_data[0U]; - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__mult_signed_result + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data [0U]), - VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)); + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)); // ALWAYS at VX_alu.v:47 - vlTOPp->Vortex__DOT__execute_alu_result = ((0x10U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? ( - (8U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? 0U - : - ((4U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((0U - == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - : - VL_MODDIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)) - : - ((0U - == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - : - VL_MODDIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((0U - == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 0xffffffffU - : - VL_DIV_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)) - : - ((0U - == vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 0xffffffffU - : - VL_DIVS_III(32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)))) - : - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? (IData)( - (((QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U])) - * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - >> 0x20U)) - : (IData)( - (((((QData)((IData)( - VL_NEGATE_I((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( (1U - & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data + & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data [0U] >> 0x1fU)))))) - << 0x20U) - | (QData)((IData)( - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U]))) - * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - >> 0x20U))) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? (IData)( - (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__mult_signed_result - >> 0x20U)) - : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__mult_signed_result))))) - : ( - (8U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U]) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data + [0U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:47 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U]) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data + [0U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))))); + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] + = vlTOPp->Vortex__DOT__execute_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] + = vlTOPp->Vortex__DOT__execute_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) ? - ((4U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? vlTOPp->Vortex__DOT__csr_decode_csr_data - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? vlTOPp->Vortex__DOT__csr_decode_csr_data - : - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC - + - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed - << 0xcU)))) - : - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed - << 0xcU) - : - ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - >= vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 0U - : 0xffffffffU)) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2 - & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U]) - : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - | vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)))) + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] : - ((4U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - VL_SHIFTRS_III(32,32,5, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], - (0x1fU - & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)) - : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - >> - (0x1fU - & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - ^ vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - : - ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - < vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 1U - : 0U))) - : - ((2U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (VL_LTS_III(1,32,32, - vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - ? 1U - : 0U) - : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - << - (0x1fU - & vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2))) - : - ((1U - & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) - ? - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - - vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2) - : - (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data - [0U] - + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2)))))); + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [0U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [0U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [0U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [0U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [0U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [0U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [0U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [0U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [0U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [0U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]))); + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] - = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)) - ? ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out - : vlTOPp->Vortex__DOT__execute_alu_result) - : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next - : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) - ? vlTOPp->in_cache_driver_out_data - : vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result)) - : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next - : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result - : vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result)) - : 0xdeadbeefU))) : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register); - vlTOPp->Vortex__DOT__vx_decode__DOT__internal_rd1 + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register + [0U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[2U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register + [1U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[0U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC - : ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)) - ? ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out - : vlTOPp->Vortex__DOT__execute_alu_result) - : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next - : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) - ? vlTOPp->in_cache_driver_out_data - : vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result)) - : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next - : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result - : vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result)) - : 0xdeadbeefU))) : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register)); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_decode__DOT__internal_rd1; + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register + [0U])); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register + [1U])); + vlTOPp->Vortex__DOT__decode_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + [3U]; + vlTOPp->Vortex__DOT__decode_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + [2U]; vlTOPp->Vortex__DOT__decode_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data [1U]; vlTOPp->Vortex__DOT__decode_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[3U] + = vlTOPp->Vortex__DOT__decode_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2U] + = vlTOPp->Vortex__DOT__decode_reg_data[2U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[1U] = vlTOPp->Vortex__DOT__decode_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[0U] = vlTOPp->Vortex__DOT__decode_reg_data[0U]; } -VL_INLINE_OPT void VVortex::_combo__TOP__8(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__8\n"); ); +VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__9\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [0U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [0U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [0U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [0U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [0U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [0U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [0U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [0U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [0U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [0U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]))); + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [0U]; vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] - = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)) - ? ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out - : vlTOPp->Vortex__DOT__execute_alu_result) - : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next - : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) - ? vlTOPp->in_cache_driver_out_data - : vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result)) - : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next - : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result - : vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result)) - : 0xdeadbeefU))) : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register); - vlTOPp->Vortex__DOT__vx_decode__DOT__internal_rd1 + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register + [0U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[2U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register + [1U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[0U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC - : ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)) - ? ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out - : vlTOPp->Vortex__DOT__execute_alu_result) - : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next - : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) - ? vlTOPp->in_cache_driver_out_data - : vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result)) - : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) - ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next - : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) - ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result - : vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result)) - : 0xdeadbeefU))) : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register)); - vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_decode__DOT__internal_rd1; + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register + [0U])); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register + [1U])); + vlTOPp->Vortex__DOT__decode_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + [3U]; + vlTOPp->Vortex__DOT__decode_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data + [2U]; vlTOPp->Vortex__DOT__decode_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data [1U]; vlTOPp->Vortex__DOT__decode_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[3U] + = vlTOPp->Vortex__DOT__decode_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2U] + = vlTOPp->Vortex__DOT__decode_reg_data[2U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[1U] = vlTOPp->Vortex__DOT__decode_reg_data[1U]; vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[0U] @@ -2145,14 +3130,15 @@ void VVortex::_eval(VVortex__Syms* __restrict vlSymsp) { if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { vlTOPp->_sequent__TOP__2(vlSymsp); } + vlTOPp->_combo__TOP__3(vlSymsp); if (((~ (IData)(vlTOPp->clk)) & (IData)(vlTOPp->__Vclklast__TOP__clk))) { - vlTOPp->_sequent__TOP__3(vlSymsp); + vlTOPp->_sequent__TOP__5(vlSymsp); } if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) { - vlTOPp->_sequent__TOP__6(vlSymsp); + vlTOPp->_sequent__TOP__7(vlSymsp); } - vlTOPp->_combo__TOP__8(vlSymsp); + vlTOPp->_combo__TOP__9(vlSymsp); // Final vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; @@ -2164,7 +3150,7 @@ void VVortex::_eval_initial(VVortex__Syms* __restrict vlSymsp) { // Body vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; - vlTOPp->_initial__TOP__5(vlSymsp); + vlTOPp->_initial__TOP__6(vlSymsp); } void VVortex::final() { @@ -2179,7 +3165,7 @@ void VVortex::_eval_settle(VVortex__Syms* __restrict vlSymsp) { VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body vlTOPp->_settle__TOP__4(vlSymsp); - vlTOPp->_settle__TOP__7(vlSymsp); + vlTOPp->_settle__TOP__8(vlSymsp); } VL_INLINE_OPT QData VVortex::_change_request(VVortex__Syms* __restrict vlSymsp) { @@ -2208,55 +3194,174 @@ void VVortex::_ctor_var_reset() { clk = VL_RAND_RESET_I(1); reset = VL_RAND_RESET_I(1); fe_instruction = VL_RAND_RESET_I(32); - in_cache_driver_out_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32); + }} curr_PC = VL_RAND_RESET_I(32); - out_cache_driver_in_address = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32); + }} out_cache_driver_in_mem_read = VL_RAND_RESET_I(3); out_cache_driver_in_mem_write = VL_RAND_RESET_I(3); - out_cache_driver_in_valid = VL_RAND_RESET_I(1); - out_cache_driver_in_data = VL_RAND_RESET_I(32); - Vortex__DOT__decode_csr_address = VL_RAND_RESET_I(12); + out_cache_driver_in_valid = VL_RAND_RESET_I(2); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__fetch_valid = VL_RAND_RESET_I(2); + Vortex__DOT__decode_csr_address = VL_RAND_RESET_I(12); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__decode_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__decode_itype_immed = VL_RAND_RESET_I(32); Vortex__DOT__decode_branch_type = VL_RAND_RESET_I(3); - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__d_e_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__execute_branch_stall = VL_RAND_RESET_I(1); - Vortex__DOT__execute_alu_result = VL_RAND_RESET_I(32); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__execute_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__execute_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__e_m_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__e_m_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__memory_branch_dir = VL_RAND_RESET_I(1); Vortex__DOT__memory_branch_dest = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__memory_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__memory_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__m_w_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__m_w_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__writeback_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} Vortex__DOT__csr_decode_csr_data = VL_RAND_RESET_I(32); Vortex__DOT__forwarding_fwd_stall = VL_RAND_RESET_I(1); + Vortex__DOT__forwarding_src1_fwd = VL_RAND_RESET_I(1); + Vortex__DOT__forwarding_src2_fwd = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__forwarding_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__forwarding_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellout__vx_decode__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellout__vx_execute__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_execute__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellinp__vx_execute__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__use_rd2[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_memory__in_rd2[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_memory__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_writeback__out_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} Vortex__DOT__vx_fetch__DOT__stall_reg = VL_RAND_RESET_I(1); Vortex__DOT__vx_fetch__DOT__delay_reg = VL_RAND_RESET_I(1); Vortex__DOT__vx_fetch__DOT__old = VL_RAND_RESET_I(32); @@ -2268,22 +3373,33 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_fetch__DOT__PC_to_use = VL_RAND_RESET_I(32); Vortex__DOT__vx_fetch__DOT__stall = VL_RAND_RESET_I(1); Vortex__DOT__vx_fetch__DOT__temp_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_fetch__DOT__valid = VL_RAND_RESET_I(2); Vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32); Vortex__DOT__vx_f_d_reg__DOT__curr_PC = VL_RAND_RESET_I(32); - Vortex__DOT__vx_f_d_reg__DOT__valid = VL_RAND_RESET_I(1); - Vortex__DOT__vx_decode__DOT__rd1_register = VL_RAND_RESET_I(32); - Vortex__DOT__vx_decode__DOT__rd2_register = VL_RAND_RESET_I(32); + Vortex__DOT__vx_f_d_reg__DOT__valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__rd2_register[__Vi0] = VL_RAND_RESET_I(32); + }} Vortex__DOT__vx_decode__DOT__is_itype = VL_RAND_RESET_I(1); Vortex__DOT__vx_decode__DOT__is_csr = VL_RAND_RESET_I(1); Vortex__DOT__vx_decode__DOT__alu_tempp = VL_RAND_RESET_I(12); Vortex__DOT__vx_decode__DOT__mul_alu = VL_RAND_RESET_I(5); - Vortex__DOT__vx_decode__DOT__internal_rd1 = VL_RAND_RESET_I(32); Vortex__DOT__vx_decode__DOT__temp_final_alu = VL_RAND_RESET_I(5); + Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data = VL_RAND_RESET_I(32); { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5); - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_d_e_reg__DOT__alu_op = VL_RAND_RESET_I(5); @@ -2301,19 +3417,29 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_d_e_reg__DOT__curr_PC = VL_RAND_RESET_I(32); Vortex__DOT__vx_d_e_reg__DOT__jal = VL_RAND_RESET_I(1); Vortex__DOT__vx_d_e_reg__DOT__jal_offset = VL_RAND_RESET_I(32); - Vortex__DOT__vx_d_e_reg__DOT__valid = VL_RAND_RESET_I(1); - Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[__Vi0] = VL_RAND_RESET_I(32); }} + Vortex__DOT__vx_d_e_reg__DOT__valid_z = VL_RAND_RESET_I(2); + Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1); + Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { - Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); }} - Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32); - Vortex__DOT__vx_execute__DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64); - Vortex__DOT__vx_e_m_reg__DOT__alu_result = VL_RAND_RESET_I(32); - Vortex__DOT__vx_e_m_reg__DOT__rd = VL_RAND_RESET_I(5); + Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64); + Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_e_m_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_e_m_reg__DOT__rd = VL_RAND_RESET_I(5); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { Vortex__DOT__vx_e_m_reg__DOT__reg_data[__Vi0] = VL_RAND_RESET_I(32); }} Vortex__DOT__vx_e_m_reg__DOT__wb = VL_RAND_RESET_I(2); @@ -2328,19 +3454,35 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_e_m_reg__DOT__branch_type = VL_RAND_RESET_I(3); Vortex__DOT__vx_e_m_reg__DOT__jal = VL_RAND_RESET_I(1); Vortex__DOT__vx_e_m_reg__DOT__jal_dest = VL_RAND_RESET_I(32); - Vortex__DOT__vx_e_m_reg__DOT__valid = VL_RAND_RESET_I(1); - Vortex__DOT__vx_m_w_reg__DOT__alu_result = VL_RAND_RESET_I(32); - Vortex__DOT__vx_m_w_reg__DOT__mem_result = VL_RAND_RESET_I(32); + Vortex__DOT__vx_e_m_reg__DOT__valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_m_w_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_m_w_reg__DOT__mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} Vortex__DOT__vx_m_w_reg__DOT__rd = VL_RAND_RESET_I(5); Vortex__DOT__vx_m_w_reg__DOT__wb = VL_RAND_RESET_I(2); Vortex__DOT__vx_m_w_reg__DOT__PC_next = VL_RAND_RESET_I(32); - Vortex__DOT__vx_m_w_reg__DOT__valid = VL_RAND_RESET_I(1); + Vortex__DOT__vx_m_w_reg__DOT__valid = VL_RAND_RESET_I(2); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_writeback__DOT__out_pc_data[__Vi0] = VL_RAND_RESET_I(32); + }} Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd = VL_RAND_RESET_I(1); Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd = VL_RAND_RESET_I(1); Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd = VL_RAND_RESET_I(1); Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd = VL_RAND_RESET_I(1); Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd = VL_RAND_RESET_I(1); Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[__Vi0] = VL_RAND_RESET_I(32); + }} { int __Vi0=0; for (; __Vi0<4096; ++__Vi0) { Vortex__DOT__vx_csr_handler__DOT__csr[__Vi0] = VL_RAND_RESET_I(12); }} diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h index e831cf88..fe11b41f 100644 --- a/rtl/obj_dir/VVortex.h +++ b/rtl/obj_dir/VVortex.h @@ -25,28 +25,32 @@ VL_MODULE(VVortex) { VL_IN8(reset,0,0); VL_OUT8(out_cache_driver_in_mem_read,2,0); VL_OUT8(out_cache_driver_in_mem_write,2,0); - VL_OUT8(out_cache_driver_in_valid,0,0); + VL_OUT8(out_cache_driver_in_valid,1,0); VL_IN(fe_instruction,31,0); - VL_IN(in_cache_driver_out_data,31,0); VL_OUT(curr_PC,31,0); - VL_OUT(out_cache_driver_in_address,31,0); - VL_OUT(out_cache_driver_in_data,31,0); + VL_IN(in_cache_driver_out_data[2],31,0); + VL_OUT(out_cache_driver_in_address[2],31,0); + VL_OUT(out_cache_driver_in_data[2],31,0); // LOCAL SIGNALS // Internals; generally not touched by application code // Anonymous structures to workaround compiler member-count bugs struct { // Begin mtask footprint all: + VL_SIG8(Vortex__DOT__fetch_valid,1,0); VL_SIG8(Vortex__DOT__decode_branch_type,2,0); VL_SIG8(Vortex__DOT__execute_branch_stall,0,0); VL_SIG8(Vortex__DOT__memory_branch_dir,0,0); VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0); + VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0); + VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall_reg,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__delay_reg,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__state,4,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0); - VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,1,0); + VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid,1,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0); @@ -60,7 +64,8 @@ VL_MODULE(VVortex) { VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0); - VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid,0,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid,1,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z,1,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0); @@ -69,10 +74,10 @@ VL_MODULE(VVortex) { VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0); - VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid,0,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid,1,0); VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0); VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0); - VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid,0,0); + VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid,1,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0); @@ -85,7 +90,6 @@ VL_MODULE(VVortex) { VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0); VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0); VL_SIG(Vortex__DOT__decode_itype_immed,31,0); - VL_SIG(Vortex__DOT__execute_alu_result,31,0); VL_SIG(Vortex__DOT__memory_branch_dest,31,0); VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0); VL_SIG(Vortex__DOT__vx_fetch__DOT__old,31,0); @@ -96,38 +100,54 @@ VL_MODULE(VVortex) { VL_SIG(Vortex__DOT__vx_fetch__DOT__temp_PC,31,0); VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0); VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0); - VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register,31,0); - VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register,31,0); - VL_SIG(Vortex__DOT__vx_decode__DOT__internal_rd1,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0); }; struct { + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0); - VL_SIG(Vortex__DOT__vx_execute__DOT__vx_alu__DOT__ALU_in2,31,0); - VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0); - VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result,31,0); - VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result,31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0); - VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu__DOT__mult_signed_result,63,0); + VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); + VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0); - VL_SIG(Vortex__DOT__decode_reg_data[2],31,0); - VL_SIG(Vortex__DOT__d_e_reg_data[2],31,0); - VL_SIG(Vortex__DOT__execute_reg_data[2],31,0); - VL_SIG(Vortex__DOT__e_m_reg_data[2],31,0); - VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[32],31,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[2],31,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0); - VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[2],31,0); + VL_SIG(Vortex__DOT__decode_reg_data[4],31,0); + VL_SIG(Vortex__DOT__d_e_reg_data[4],31,0); + VL_SIG(Vortex__DOT__execute_alu_result[2],31,0); + VL_SIG(Vortex__DOT__execute_reg_data[4],31,0); + VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0); + VL_SIG(Vortex__DOT__e_m_reg_data[4],31,0); + VL_SIG(Vortex__DOT__memory_alu_result[2],31,0); + VL_SIG(Vortex__DOT__memory_mem_result[2],31,0); + VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0); + VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0); + VL_SIG(Vortex__DOT__writeback_write_data[2],31,0); + VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0); + VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0); + VL_SIG(Vortex__DOT__use_rd2[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[32],31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0); + VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0); + VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0); + VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0); + VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0); + VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0); VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0); }; @@ -137,14 +157,48 @@ VL_MODULE(VVortex) { VL_SIG8(__Vtableidx1,2,0); VL_SIG8(__Vclklast__TOP__clk,0,0); VL_SIG8(__Vclklast__TOP__reset,0,0); - VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2],31,0); - VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2],31,0); - VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu__in_reg_data[2],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[2],31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[2],31,0); static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0); // INTERNAL VARIABLES @@ -179,7 +233,8 @@ VL_MODULE(VVortex) { private: static QData _change_request(VVortex__Syms* __restrict vlSymsp); public: - static void _combo__TOP__8(VVortex__Syms* __restrict vlSymsp); + static void _combo__TOP__3(VVortex__Syms* __restrict vlSymsp); + static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp); private: void _ctor_var_reset(); public: @@ -191,13 +246,13 @@ VL_MODULE(VVortex) { public: static void _eval_initial(VVortex__Syms* __restrict vlSymsp); static void _eval_settle(VVortex__Syms* __restrict vlSymsp); - static void _initial__TOP__5(VVortex__Syms* __restrict vlSymsp); + static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp); - static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp); - static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp); static void _settle__TOP__4(VVortex__Syms* __restrict vlSymsp); - static void _settle__TOP__7(VVortex__Syms* __restrict vlSymsp); + static void _settle__TOP__8(VVortex__Syms* __restrict vlSymsp); } VL_ATTR_ALIGNED(128); #endif // guard diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a index d77cb3e51a39c002ac3a2b47a3354ebe3cf4b5e2..e0884b0ced04ab9a1ea4e83214fdd8f98a0961ff 100644 GIT binary patch literal 55840 zcmdVD4SZGCbtifiV;dP_DJ@CJ)Ez`k5|S84;>!?|SOQ&hO%MnhFt#BV48o9#k6_`F zjIpmI1ov=Ihh`ul6J|;}^f&w(-h|{ij_gNl$!3u3&{(c{37w&>?9xO^NTQ^E4Nhrz z|NmNRpO1TwBuG5->s*_&_Fj9fwfA28^Q^tk(!@DywyoXpiJNY%`smckittx8W5%?Z zcTAl*byh{ijLNA<(B!Jh%9+!rS5#C@n>|yhSKpM)-hST$b+zfcQ{nFtf=^wSN_AYH zN(~rfD&yk~RvKJo&@=e7!3zd|r$qT`46ZS_-{A8Ge`avPJCuI0!6yxV&EV?>Cs?_r z8NADjegHa)y0n_arNKAW9(P1LhTpq`OkyJ5}dM;fx*8a}hV;nAj% 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zWIC`9$LGvm_)u;RDN{3Nk)VU*^$*tM;e#rYe3hP~%N&a*+4G#**g_{Uhe@$S)FmE@ z&8tZ~Tj)Fy)^Mq(-Z4gHBmY9awhI9bdX&<=0C86No;x+I$KeB>slbsBZsIQ2^CWliA6X? zTefof`gQr!@Np`Rhr;aG!Wag`LI_y-@RS7p4{0*}4#;U){CIOyMZzvSH4iRKB%a)m zSlYA%XLgAMr&q0SPAqO-??h^6%}O+FSkkn%CBb}mKwe_`h7F0eP3xXmgN1x$%TtLb Lr{vMWwvPN?PO_H= diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat index ad661920..842d4aec 100644 --- a/rtl/obj_dir/VVortex__verFiles.dat +++ b/rtl/obj_dir/VVortex__verFiles.dat @@ -1,26 +1,26 @@ # DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp" S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" -S 2782 12889318286 1553658869 0 1553658869 0 "VX_alu.v" +S 2782 12889318286 1553669148 0 1553669148 0 "VX_alu.v" S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v" -S 4603 12889318287 1553658869 0 1553658869 0 "VX_d_e_reg.v" -S 9346 12889318288 1553659302 0 1553659302 0 "VX_decode.v" -S 1503 12889079483 1553237629 0 1553237629 0 "VX_define.v" -S 3547 12889318289 1553658869 0 1553658869 0 "VX_e_m_reg.v" -S 2653 12889318290 1553658869 0 1553658869 0 "VX_execute.v" -S 1120 12889050060 1553236935 0 1553236935 0 "VX_f_d_reg.v" -S 3537 12889047675 1553236929 0 1553236929 0 "VX_fetch.v" -S 5020 12889086478 1553236985 0 1553236985 0 "VX_forwarding.v" -S 1578 12889085814 1553211072 0 1553211072 0 "VX_m_w_reg.v" -S 2741 12889084513 1553659625 0 1553659625 0 "VX_memory.v" +S 4759 12889318287 1553668670 0 1553668670 0 "VX_d_e_reg.v" +S 10698 12889318288 1553672118 0 1553672118 0 "VX_decode.v" +S 1551 12889079483 1553661565 0 1553661565 0 "VX_define.v" +S 3922 12889318289 1553672147 0 1553672147 0 "VX_e_m_reg.v" +S 3350 12889318290 1553669263 0 1553669263 0 "VX_execute.v" +S 1351 12889050060 1553664431 0 1553664431 0 "VX_f_d_reg.v" +S 3931 12889047675 1553672617 0 1553672617 0 "VX_fetch.v" +S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v" +S 1658 12889085814 1553671325 0 1553671325 0 "VX_m_w_reg.v" +S 2771 12889084513 1553670938 0 1553670938 0 "VX_memory.v" S 1000 12889070228 1553659195 0 1553659195 0 "VX_register_file.v" -S 806 12889086287 1553236964 0 1553236964 0 "VX_writeback.v" -S 12860 12889318291 1553659648 0 1553659648 0 "Vortex.v" -T 101094 12889318706 1553659652 0 1553659652 0 "obj_dir/VVortex.cpp" -T 8985 12889318705 1553659652 0 1553659652 0 "obj_dir/VVortex.h" -T 1800 12889318708 1553659652 0 1553659652 0 "obj_dir/VVortex.mk" -T 530 12889318704 1553659652 0 1553659652 0 "obj_dir/VVortex__Syms.cpp" -T 711 12889318703 1553659652 0 1553659652 0 "obj_dir/VVortex__Syms.h" -T 464 12889318709 1553659652 0 1553659652 0 "obj_dir/VVortex__ver.d" -T 0 0 1553659652 0 1553659652 0 "obj_dir/VVortex__verFiles.dat" -T 1159 12889318707 1553659652 0 1553659652 0 "obj_dir/VVortex_classes.mk" +S 1010 12889086287 1553671609 0 1553671609 0 "VX_writeback.v" +S 15561 12889318291 1553672234 0 1553672234 0 "Vortex.v" +T 173538 12889376662 1553672623 0 1553672623 0 "obj_dir/VVortex.cpp" +T 13367 12889376661 1553672623 0 1553672623 0 "obj_dir/VVortex.h" +T 1800 12889376664 1553672623 0 1553672623 0 "obj_dir/VVortex.mk" +T 530 12889376660 1553672623 0 1553672623 0 "obj_dir/VVortex__Syms.cpp" +T 711 12889376659 1553672623 0 1553672623 0 "obj_dir/VVortex__Syms.h" +T 464 12889376665 1553672623 0 1553672623 0 "obj_dir/VVortex__ver.d" +T 0 0 1553672623 0 1553672623 0 "obj_dir/VVortex__verFiles.dat" +T 1159 12889376663 1553672623 0 1553672623 0 "obj_dir/VVortex_classes.mk" diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o index 2f052a38101ec02d1a178cc7659a93b37578ad30..7e8cd0cb6568be3ed354967b4182ff86234178f1 100644 GIT binary patch delta 6338 zcmZvh30PF+8ppqL1O&9kB?2^-aX~;2l18|pXpE98D7fMRTJBp)E@d+YB*R=2{4}*R zF}+!?=%_4Dmxh~Nu&gktFs)STDwQ{_TitBo{@;1OLF#dyVSeZTf8X!@mUF%{&T-2R ztxo^9RbgU>WtGDHTHT5{ud-K)GHElxbQweO{$ptBnm_c7TJcHRkohLQwr0c}0s4xOtG>nG7-SD5CBT zlJ)T5ltXO0S~F`9r9t16>-G5Hb|=`K?9a?E<)}-ZL$u}-A$$?g@fU=@TIg56n@)49 zzPj$aTTb-uuYKSw^iFN7+q%hy_7VE5&9Y60etPs~Y3Yy()49DvgHFM90U0DO2GnTU z1?RrNOikb9aJCMfrRj+U&iS2YY1&WDcRIsEoW2uXI_YeJ4#_>mKO3UWjCS^>vI6%!|F<)YRyUIymLf|c zgVSnExoxQjhovUjkuOlfwx+Ex<^GI@)s}jEikx-zx+&)hj#^|n((COXJJOCt+S4zq zh8`f7= zm^@aE%FII<*PSw`W4E{*7S~qOr zt;ICCb1ze#xy9J;+TFyvHS})L5Tm`*uxpF?(vE7;r6ax0{&98Eu^?&d8N2{7tXZA= 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forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01849 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-andi.hex **************** -# Dynamic Instructions: 246 -# of total cycles: 257 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.04472 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-auipc.hex **************** -# Dynamic Instructions: 65 -# of total cycles: 76 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.16923 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-beq.hex **************** -# Dynamic Instructions: 431 -# of total cycles: 442 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.02552 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-bge.hex **************** -# Dynamic Instructions: 467 -# of total cycles: 478 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.02355 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-bgeu.hex **************** -# Dynamic Instructions: 492 -# of total cycles: 503 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.02236 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-blt.hex **************** -# Dynamic Instructions: 431 -# of total cycles: 442 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.02552 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-bltu.hex **************** -# Dynamic Instructions: 456 -# of total cycles: 467 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.02412 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-bne.hex **************** -# Dynamic Instructions: 431 -# of total cycles: 442 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.02552 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-jal.hex **************** -# Dynamic Instructions: 61 -# of total cycles: 72 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.18033 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-jalr.hex **************** -# Dynamic Instructions: 138 -# of total cycles: 149 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.07971 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-lb.hex **************** -# Dynamic Instructions: 331 -# of total cycles: 342 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03323 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-lbu.hex **************** -# Dynamic Instructions: 331 -# of total cycles: 342 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03323 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-lh.hex **************** -# Dynamic Instructions: 339 -# of total cycles: 350 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03245 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-lhu.hex **************** -# Dynamic Instructions: 343 -# of total cycles: 354 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03207 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-lui.hex **************** -# Dynamic Instructions: 73 -# of total cycles: 84 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.15068 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-lw.hex **************** -# Dynamic Instructions: 346 -# of total cycles: 357 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03179 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-or.hex **************** -# Dynamic Instructions: 598 -# of total cycles: 609 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01839 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-ori.hex **************** -# Dynamic Instructions: 253 -# of total cycles: 264 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.04348 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-sb.hex **************** -# Dynamic Instructions: 571 -# of total cycles: 582 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01926 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-sh.hex **************** -# Dynamic Instructions: 603 -# of total cycles: 614 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01824 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-simple.hex **************** -# Dynamic Instructions: 37 -# of total cycles: 48 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.2973 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-sll.hex **************** -# Dynamic Instructions: 633 -# of total cycles: 644 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01738 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-slli.hex **************** -# Dynamic Instructions: 311 -# of total cycles: 322 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03537 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-slt.hex **************** -# Dynamic Instructions: 591 -# of total cycles: 602 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01861 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-slti.hex **************** -# Dynamic Instructions: 307 -# of total cycles: 318 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03583 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-sltiu.hex **************** -# Dynamic Instructions: 307 -# of total cycles: 318 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03583 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-sltu.hex **************** -# Dynamic Instructions: 591 -# of total cycles: 602 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01861 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-sra.hex **************** -# Dynamic Instructions: 654 -# of total cycles: 665 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01682 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-srai.hex **************** -# Dynamic Instructions: 326 -# of total cycles: 337 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03374 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-srl.hex **************** -# Dynamic Instructions: 648 -# of total cycles: 659 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01698 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-srli.hex **************** -# Dynamic Instructions: 320 -# of total cycles: 331 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.03438 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-sub.hex **************** -# Dynamic Instructions: 587 -# of total cycles: 598 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01874 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-sw.hex **************** -# Dynamic Instructions: 612 -# of total cycles: 623 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01797 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-xor.hex **************** -# Dynamic Instructions: 597 -# of total cycles: 608 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01843 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32ui-p-xori.hex **************** -# Dynamic Instructions: 255 -# of total cycles: 266 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.04314 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32um-p-div.hex **************** -# Dynamic Instructions: 112 -# of total cycles: 123 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.09821 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32um-p-divu.hex **************** -# Dynamic Instructions: 113 -# of total cycles: 124 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.09735 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32um-p-mul.hex **************** -# Dynamic Instructions: 589 -# of total cycles: 600 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.01868 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32um-p-mulh.hex **************** -# Dynamic Instructions: 585 -# of total cycles: 596 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.0188 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32um-p-mulhsu.hex **************** -# Dynamic Instructions: 585 -# of total cycles: 596 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.0188 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32um-p-mulhu.hex **************** -# Dynamic Instructions: 585 -# of total cycles: 596 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.0188 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32um-p-rem.hex **************** -# Dynamic Instructions: 112 -# of total cycles: 123 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.09821 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING - -**************** ../../emulator/riscv_tests/rv32um-p-remu.hex **************** -# Dynamic Instructions: 112 -# of total cycles: 123 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.09821 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: PASSING diff --git a/rtl/test_bench.h b/rtl/test_bench.h index 123d11a2..f88dd7e3 100644 --- a/rtl/test_bench.h +++ b/rtl/test_bench.h @@ -175,22 +175,25 @@ bool Vortex::dbus_driver() if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid) { - data_write = (uint32_t) vortex->out_cache_driver_in_data; - addr = (uint32_t) vortex->out_cache_driver_in_address; + for (unsigned curr_th = 0; curr_th < NT; curr_th++) + { + data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th]; + addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th]; - if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE) - { - data_write = ( data_write) & 0xFF; - ram.writeByte( addr, &data_write); + if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE) + { + data_write = ( data_write) & 0xFF; + ram.writeByte( addr, &data_write); - } else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE) - { - data_write = ( data_write) & 0xFFFF; - ram.writeHalf( addr, &data_write); - } else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE) - { - data_write = data_write; - ram.writeWord( addr, &data_write); + } else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE) + { + data_write = ( data_write) & 0xFFFF; + ram.writeHalf( addr, &data_write); + } else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE) + { + data_write = data_write; + ram.writeWord( addr, &data_write); + } } } @@ -198,45 +201,49 @@ bool Vortex::dbus_driver() if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid) { - addr = (uint32_t) vortex->out_cache_driver_in_address; - ram.getWord(addr, &data_read); + for (unsigned curr_th = 0; curr_th < NT; curr_th++) + { + addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th]; + ram.getWord(addr, &data_read); - if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ) - { + if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ) + { - vortex->in_cache_driver_out_data = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF); - } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ) - { + } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ) + { - vortex->in_cache_driver_out_data = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF); - } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ) - { - // printf("Reading mem - Addr: %h = %h\n", addr, data_read); - // std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n"; - std::cout << std::dec; - vortex->in_cache_driver_out_data = data_read; + } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ) + { + // printf("Reading mem - Addr: %h = %h\n", addr, data_read); + // std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n"; + std::cout << std::dec; + vortex->in_cache_driver_out_data[curr_th] = data_read; - } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ) - { + } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ) + { - vortex->in_cache_driver_out_data = (data_read & 0xFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF); - } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ) - { + } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ) + { - vortex->in_cache_driver_out_data = (data_read & 0xFFFF); + vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF); - } - else - { - vortex->in_cache_driver_out_data = 0xbabebabe; - } + } + else + { + vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; + } + } } else { - vortex->in_cache_driver_out_data = 0xbabebabe; + for (unsigned curr_th = 0; curr_th < NT; curr_th++) + vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; } return false;