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fixed L2 cache

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This commit is contained in:
Blaise Tine
2020-06-02 05:32:50 -07:00
parent e01c411b20
commit 9b186dcc6e
6 changed files with 46 additions and 37 deletions
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4
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -25,7 +25,7 @@ module VX_cache_miss_resrv #(
input wire miss_add,
input wire from_mrvq,
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`WORD_SELECT_WIDTH-1:0] miss_add_wsel,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data,
input wire[`REQS_BITS-1:0] miss_add_tid,
input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag,
@@ -46,7 +46,7 @@ module VX_cache_miss_resrv #(
input wire miss_resrv_pop,
output wire miss_resrv_valid_st0,
output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
output wire[`WORD_SELECT_WIDTH-1:0] miss_resrv_wsel_st0,
output wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_resrv_wsel_st0,
output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0,