VX_pipeline refactoring + logic analyzer

hw/opae/vortex_afu.json

@@ -5,11 +5,13 @@
       "clock-frequency-high": "auto",
       "clock-frequency-low":  "auto",
       
-      "mmio-csr-cmd":         10,      
-      "mmio-csr-status":      12,      
-      "mmio-csr-io-addr":     14,
-      "mmio-csr-mem-addr":    16,
-      "mmio-csr-data-size":   18,
+      "mmio-csr-cmd":         10,     
+      "mmio-csr-io-addr":     12,
+      "mmio-csr-mem-addr":    14,
+      "mmio-csr-data-size":   16,          
+      "mmio-csr-status":      18,   
+      "mmio-csr-scope-delay": 20,
+      "mmio-csr-scope-data":  22,
       
       "cmd-type-read":        1,
       "cmd-type-write":       2,