basic test timing + scope tracing ccip
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22
hw/rtl/cache/VX_bank.v
vendored
22
hw/rtl/cache/VX_bank.v
vendored
@@ -737,18 +737,18 @@ module VX_bank #(
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end
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`endif
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`SCOPE_ASSIGN (scope_valid_st0, qual_valid_st0);
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`SCOPE_ASSIGN (scope_valid_st1, valid_st1);
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`SCOPE_ASSIGN (scope_valid_st2, valid_st2);
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`SCOPE_ASSIGN (valid_st0, qual_valid_st0);
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`SCOPE_ASSIGN (valid_st1, valid_st1);
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`SCOPE_ASSIGN (valid_st2, valid_st2);
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`SCOPE_ASSIGN (scope_is_mrvq_st1, is_mrvq_st1);
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`SCOPE_ASSIGN (scope_miss_st1, miss_st1);
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`SCOPE_ASSIGN (scope_dirty_st1, dirty_st1);
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`SCOPE_ASSIGN (scope_force_miss_st1, force_request_miss_st1);
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`SCOPE_ASSIGN (scope_stall_pipe, stall_bank_pipe);
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`SCOPE_ASSIGN (is_mrvq_st1, is_mrvq_st1);
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`SCOPE_ASSIGN (miss_st1, miss_st1);
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`SCOPE_ASSIGN (dirty_st1, dirty_st1);
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`SCOPE_ASSIGN (force_miss_st1, force_request_miss_st1);
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`SCOPE_ASSIGN (stall_pipe, stall_bank_pipe);
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`SCOPE_ASSIGN (scope_addr_st0, `LINE_TO_BYTE_ADDR(qual_addr_st0, BANK_ID));
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`SCOPE_ASSIGN (scope_addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
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`SCOPE_ASSIGN (scope_addr_st2, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID));
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`SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(qual_addr_st0, BANK_ID));
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`SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
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`SCOPE_ASSIGN (addr_st2, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID));
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endmodule
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