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basic test timing + scope tracing ccip

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This commit is contained in:
Blaise Tine
2020-10-27 17:04:04 -04:00
parent 4bd5ee2673
commit 9a9f7955f0
16 changed files with 228 additions and 180 deletions
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16
hw/rtl/VX_config.vh
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@@ -36,13 +36,27 @@
`endif
`ifndef IO_BUS_BASE_ADDR
`define IO_BUS_BASE_ADDR 32'hFFFFFF00
`define IO_BUS_BASE_ADDR 32'hFF000000
`endif
`ifndef IO_BUS_ADDR_COUT
`define IO_BUS_ADDR_COUT 32'hFFFFFFFC
`endif
`ifndef FRAME_BUFFER_BASE_ADDR
`define FRAME_BUFFER_BASE_ADDR 32'hFF000000
`endif
`ifndef FRAME_BUFFER_WIDTH
`define FRAME_BUFFER_WIDTH 16'd1920
`endif
`ifndef FRAME_BUFFER_HEIGHT
`define FRAME_BUFFER_HEIGHT 16'd1080
`endif
`define FRAME_BUFFER_SIZE (FRAME_BUFFER_WIDTH * FRAME_BUFFER_HEIGHT)
`ifndef L2_ENABLE
`define L2_ENABLE 0
`endif

26
hw/rtl/VX_gpu_unit.v
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@@ -90,18 +90,18 @@ module VX_gpu_unit #(
// can accept new request?
assign gpu_req_if.ready = gpu_commit_if.ready;
`SCOPE_ASSIGN (scope_gpu_req_valid, gpu_req_if.valid);
`SCOPE_ASSIGN (scope_gpu_req_wid, gpu_req_if.wid);
`SCOPE_ASSIGN (scope_gpu_req_tmask, gpu_req_if.tmask);
`SCOPE_ASSIGN (scope_gpu_req_op_type, gpu_req_if.op_type);
`SCOPE_ASSIGN (scope_gpu_req_rs1, gpu_req_if.rs1_data[0]);
`SCOPE_ASSIGN (scope_gpu_req_rs2, gpu_req_if.rs2_data);
`SCOPE_ASSIGN (scope_gpu_req_ready, gpu_req_if.ready);
`SCOPE_ASSIGN (scope_gpu_rsp_valid, warp_ctl_if.valid);
`SCOPE_ASSIGN (scope_gpu_rsp_wid, warp_ctl_if.wid);
`SCOPE_ASSIGN (scope_gpu_rsp_tmc, warp_ctl_if.tmc);
`SCOPE_ASSIGN (scope_gpu_rsp_wspawn, warp_ctl_if.wspawn);
`SCOPE_ASSIGN (scope_gpu_rsp_split, warp_ctl_if.split);
`SCOPE_ASSIGN (scope_gpu_rsp_barrier, warp_ctl_if.barrier);
`SCOPE_ASSIGN (gpu_req_fire, gpu_req_if.valid && gpu_req_if.ready);
`SCOPE_ASSIGN (gpu_req_wid, gpu_req_if.wid);
`SCOPE_ASSIGN (gpu_req_tmask, gpu_req_if.tmask);
`SCOPE_ASSIGN (gpu_req_op_type, gpu_req_if.op_type);
`SCOPE_ASSIGN (gpu_req_rs1, gpu_req_if.rs1_data[0]);
`SCOPE_ASSIGN (gpu_req_rs2, gpu_req_if.rs2_data);
`SCOPE_ASSIGN (gpu_rsp_valid, warp_ctl_if.valid);
`SCOPE_ASSIGN (gpu_rsp_wid, warp_ctl_if.wid);
`SCOPE_ASSIGN (gpu_rsp_tmc, warp_ctl_if.tmc);
`SCOPE_ASSIGN (gpu_rsp_wspawn, warp_ctl_if.wspawn);
`SCOPE_ASSIGN (gpu_rsp_split, warp_ctl_if.split);
`SCOPE_ASSIGN (gpu_rsp_barrier, warp_ctl_if.barrier);
endmodule

16
hw/rtl/VX_icache_stage.v
View File

@@ -60,16 +60,14 @@ module VX_icache_stage #(
// Can accept new response?
assign icache_rsp_if.ready = ifetch_rsp_if.ready;
`SCOPE_ASSIGN (scope_icache_req_valid, icache_req_if.valid);
`SCOPE_ASSIGN (scope_icache_req_wid, ifetch_req_if.wid);
`SCOPE_ASSIGN (scope_icache_req_addr, {icache_req_if.addr, 2'b0});
`SCOPE_ASSIGN (scope_icache_req_tag, req_tag);
`SCOPE_ASSIGN (scope_icache_req_ready, icache_req_if.ready);
`SCOPE_ASSIGN (icache_req_fire, icache_req_fire);
`SCOPE_ASSIGN (icache_req_wid, ifetch_req_if.wid);
`SCOPE_ASSIGN (icache_req_addr, {icache_req_if.addr, 2'b0});
`SCOPE_ASSIGN (icache_req_tag, req_tag);
`SCOPE_ASSIGN (scope_icache_rsp_valid, icache_rsp_if.valid);
`SCOPE_ASSIGN (scope_icache_rsp_data, icache_rsp_if.data);
`SCOPE_ASSIGN (scope_icache_rsp_tag, rsp_tag);
`SCOPE_ASSIGN (scope_icache_rsp_ready, icache_rsp_if.ready);
`SCOPE_ASSIGN (icache_rsp_fire, icache_rsp_if.valid && icache_rsp_if.ready);
`SCOPE_ASSIGN (icache_rsp_data, icache_rsp_if.data);
`SCOPE_ASSIGN (icache_rsp_tag, rsp_tag);
`ifdef DBG_PRINT_CORE_ICACHE
always @(posedge clk) begin

60
hw/rtl/VX_issue.v
View File

@@ -100,38 +100,38 @@ module VX_issue #(
.gpu_req_if (gpu_req_if)
);
`SCOPE_ASSIGN (scope_issue_valid, ibuf_deq_if.valid);
`SCOPE_ASSIGN (scope_issue_wid, ibuf_deq_if.wid);
`SCOPE_ASSIGN (scope_issue_tmask, ibuf_deq_if.tmask);
`SCOPE_ASSIGN (scope_issue_pc, ibuf_deq_if.PC);
`SCOPE_ASSIGN (scope_issue_ex_type, ibuf_deq_if.ex_type);
`SCOPE_ASSIGN (scope_issue_op_type, ibuf_deq_if.op_type);
`SCOPE_ASSIGN (scope_issue_op_mod, ibuf_deq_if.op_mod);
`SCOPE_ASSIGN (scope_issue_wb, ibuf_deq_if.wb);
`SCOPE_ASSIGN (scope_issue_rd, ibuf_deq_if.rd);
`SCOPE_ASSIGN (scope_issue_rs1, ibuf_deq_if.rs1);
`SCOPE_ASSIGN (scope_issue_rs2, ibuf_deq_if.rs2);
`SCOPE_ASSIGN (scope_issue_rs3, ibuf_deq_if.rs3);
`SCOPE_ASSIGN (scope_issue_imm, ibuf_deq_if.imm);
`SCOPE_ASSIGN (scope_issue_rs1_is_pc, ibuf_deq_if.rs1_is_PC);
`SCOPE_ASSIGN (scope_issue_rs2_is_imm, ibuf_deq_if.rs2_is_imm);
`SCOPE_ASSIGN (scope_issue_ready, ibuf_deq_if.ready);
`SCOPE_ASSIGN (scope_scoreboard_delay, scoreboard_delay);
`SCOPE_ASSIGN (scope_gpr_delay, ~gpr_req_if.ready);
`SCOPE_ASSIGN (scope_execute_delay, ~execute_if.ready);
`SCOPE_ASSIGN (issue_fire, ibuf_deq_if.valid && ibuf_deq_if.ready);
`SCOPE_ASSIGN (issue_wid, ibuf_deq_if.wid);
`SCOPE_ASSIGN (issue_tmask, ibuf_deq_if.tmask);
`SCOPE_ASSIGN (issue_pc, ibuf_deq_if.PC);
`SCOPE_ASSIGN (issue_ex_type, ibuf_deq_if.ex_type);
`SCOPE_ASSIGN (issue_op_type, ibuf_deq_if.op_type);
`SCOPE_ASSIGN (issue_op_mod, ibuf_deq_if.op_mod);
`SCOPE_ASSIGN (issue_wb, ibuf_deq_if.wb);
`SCOPE_ASSIGN (issue_rd, ibuf_deq_if.rd);
`SCOPE_ASSIGN (issue_rs1, ibuf_deq_if.rs1);
`SCOPE_ASSIGN (issue_rs2, ibuf_deq_if.rs2);
`SCOPE_ASSIGN (issue_rs3, ibuf_deq_if.rs3);
`SCOPE_ASSIGN (issue_imm, ibuf_deq_if.imm);
`SCOPE_ASSIGN (issue_rs1_is_pc, ibuf_deq_if.rs1_is_PC);
`SCOPE_ASSIGN (issue_rs2_is_imm, ibuf_deq_if.rs2_is_imm);
`SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay);
`SCOPE_ASSIGN (gpr_delay, ~gpr_req_if.ready);
`SCOPE_ASSIGN (execute_delay, ~execute_if.ready);
`SCOPE_ASSIGN (scope_gpr_rsp_valid, gpr_rsp_if.valid);
`SCOPE_ASSIGN (scope_gpr_rsp_wid, gpr_rsp_if.wid);
`SCOPE_ASSIGN (scope_gpr_rsp_pc, gpr_rsp_if.PC);
`SCOPE_ASSIGN (scope_gpr_rsp_a, gpr_rsp_if.rs1_data);
`SCOPE_ASSIGN (scope_gpr_rsp_b, gpr_rsp_if.rs2_data);
`SCOPE_ASSIGN (scope_gpr_rsp_c, gpr_rsp_if.rs3_data);
`SCOPE_ASSIGN (gpr_rsp_valid, gpr_rsp_if.valid);
`SCOPE_ASSIGN (gpr_rsp_wid, gpr_rsp_if.wid);
`SCOPE_ASSIGN (gpr_rsp_pc, gpr_rsp_if.PC);
`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data);
`SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data);
`SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data);
`SCOPE_ASSIGN (scope_writeback_valid, writeback_if.valid);
`SCOPE_ASSIGN (scope_writeback_wid, writeback_if.wid);
`SCOPE_ASSIGN (scope_writeback_pc, writeback_if.PC);
`SCOPE_ASSIGN (scope_writeback_rd, writeback_if.rd);
`SCOPE_ASSIGN (scope_writeback_data, writeback_if.data);
`SCOPE_ASSIGN (writeback_valid, writeback_if.valid);
`SCOPE_ASSIGN (writeback_wid, writeback_if.wid);
`SCOPE_ASSIGN (writeback_pc, writeback_if.PC);
`SCOPE_ASSIGN (writeback_rd, writeback_if.rd);
`SCOPE_ASSIGN (writeback_data, writeback_if.data);
`ifdef DBG_PRINT_PIPELINE
always @(posedge clk) begin

24
hw/rtl/VX_lsu_unit.v
View File

@@ -192,20 +192,18 @@ module VX_lsu_unit #(
assign dcache_rsp_if.ready = ~(stall_out || mem_rsp_stall);
// scope registration
`SCOPE_ASSIGN (scope_dcache_req_valid, dcache_req_if.valid);
`SCOPE_ASSIGN (scope_dcache_req_addr, req_address);
`SCOPE_ASSIGN (scope_dcache_req_rw, req_rw);
`SCOPE_ASSIGN (scope_dcache_req_byteen,dcache_req_if.byteen);
`SCOPE_ASSIGN (scope_dcache_req_data, dcache_req_if.data);
`SCOPE_ASSIGN (scope_dcache_req_tag, req_tag);
`SCOPE_ASSIGN (scope_dcache_req_ready, dcache_req_if.ready);
`SCOPE_ASSIGN (scope_dcache_req_wid, req_wid);
`SCOPE_ASSIGN (scope_dcache_req_pc, req_pc);
`SCOPE_ASSIGN (dcache_req_fire, dcache_req_if.valid & {`NUM_THREADS{dcache_req_if.ready}});
`SCOPE_ASSIGN (dcache_req_wid, req_wid);
`SCOPE_ASSIGN (dcache_req_pc, req_pc);
`SCOPE_ASSIGN (dcache_req_addr, req_address);
`SCOPE_ASSIGN (dcache_req_rw, req_rw);
`SCOPE_ASSIGN (dcache_req_byteen,dcache_req_if.byteen);
`SCOPE_ASSIGN (dcache_req_data, dcache_req_if.data);
`SCOPE_ASSIGN (dcache_req_tag, req_tag);
`SCOPE_ASSIGN (scope_dcache_rsp_valid, dcache_rsp_if.valid);
`SCOPE_ASSIGN (scope_dcache_rsp_data, dcache_rsp_if.data);
`SCOPE_ASSIGN (scope_dcache_rsp_tag, rsp_tag);
`SCOPE_ASSIGN (scope_dcache_rsp_ready, dcache_rsp_if.ready);
`SCOPE_ASSIGN (dcache_rsp_fire, dcache_rsp_if.valid & {`NUM_THREADS{dcache_rsp_if.ready}});
`SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data);
`SCOPE_ASSIGN (dcache_rsp_tag, rsp_tag);
`ifdef DBG_PRINT_CORE_DCACHE
always @(posedge clk) begin

4
hw/rtl/VX_scope.vh
View File

@@ -5,7 +5,7 @@
`include "scope-defs.vh"
`define SCOPE_ASSIGN(d,s) assign d = s
`define SCOPE_ASSIGN(d,s) assign scope_``d = s
`else
@@ -35,7 +35,7 @@
`define SCOPE_BIND_Vortex_cluster(__i__)
`define SCOPE_BIND_top_vortex
`define SCOPE_BIND_afu_vortex
`define SCOPE_IO_VX_lsu_unit

12
hw/rtl/VX_warp_sched.v
View File

@@ -250,11 +250,11 @@ module VX_warp_sched #(
assign busy = (active_warps != 0);
`SCOPE_ASSIGN (scope_wsched_scheduled_warp, scheduled_warp);
`SCOPE_ASSIGN (scope_wsched_active_warps, active_warps);
`SCOPE_ASSIGN (scope_wsched_schedule_table, schedule_table);
`SCOPE_ASSIGN (scope_wsched_schedule_ready, schedule_ready);
`SCOPE_ASSIGN (scope_wsched_warp_to_schedule, warp_to_schedule);
`SCOPE_ASSIGN (scope_wsched_warp_pc, warp_pc);
`SCOPE_ASSIGN (wsched_scheduled_warp, scheduled_warp);
`SCOPE_ASSIGN (wsched_active_warps, active_warps);
`SCOPE_ASSIGN (wsched_schedule_table, schedule_table);
`SCOPE_ASSIGN (wsched_schedule_ready, schedule_ready);
`SCOPE_ASSIGN (wsched_warp_to_schedule, warp_to_schedule);
`SCOPE_ASSIGN (wsched_warp_pc, warp_pc);
endmodule

26
hw/rtl/Vortex.v
View File

@@ -456,6 +456,32 @@ module Vortex (
);
end
`SCOPE_ASSIGN (reset, reset);
`SCOPE_ASSIGN (dram_req_fire, dram_req_valid && dram_req_ready);
`SCOPE_ASSIGN (dram_req_addr, {dram_req_addr, 4'b0});
`SCOPE_ASSIGN (dram_req_rw, dram_req_rw);
`SCOPE_ASSIGN (dram_req_byteen,dram_req_byteen);
`SCOPE_ASSIGN (dram_req_data, dram_req_data);
`SCOPE_ASSIGN (dram_req_tag, dram_req_tag);
`SCOPE_ASSIGN (dram_rsp_fire, dram_rsp_valid && dram_rsp_ready);
`SCOPE_ASSIGN (dram_rsp_data, dram_rsp_data);
`SCOPE_ASSIGN (dram_rsp_tag, dram_rsp_tag);
`SCOPE_ASSIGN (snp_req_fire, snp_req_valid && snp_req_ready);
`SCOPE_ASSIGN (snp_req_addr, {snp_req_addr, 4'b0});
`SCOPE_ASSIGN (snp_req_invalidate, snp_req_invalidate);
`SCOPE_ASSIGN (snp_req_tag, snp_req_tag);
`SCOPE_ASSIGN (snp_rsp_fire, snp_rsp_valid && snp_rsp_ready);
`SCOPE_ASSIGN (snp_rsp_tag, snp_rsp_tag);
`SCOPE_ASSIGN (snp_rsp_fire, snp_rsp_valid && snp_rsp_ready);
`SCOPE_ASSIGN (snp_rsp_tag, snp_rsp_tag);
`SCOPE_ASSIGN (busy, busy);
`ifdef DBG_PRINT_DRAM
always @(posedge clk) begin
if (dram_req_valid && dram_req_ready) begin

22
hw/rtl/cache/VX_bank.v vendored
View File

@@ -737,18 +737,18 @@ module VX_bank #(
end
`endif
`SCOPE_ASSIGN (scope_valid_st0, qual_valid_st0);
`SCOPE_ASSIGN (scope_valid_st1, valid_st1);
`SCOPE_ASSIGN (scope_valid_st2, valid_st2);
`SCOPE_ASSIGN (valid_st0, qual_valid_st0);
`SCOPE_ASSIGN (valid_st1, valid_st1);
`SCOPE_ASSIGN (valid_st2, valid_st2);
`SCOPE_ASSIGN (scope_is_mrvq_st1, is_mrvq_st1);
`SCOPE_ASSIGN (scope_miss_st1, miss_st1);
`SCOPE_ASSIGN (scope_dirty_st1, dirty_st1);
`SCOPE_ASSIGN (scope_force_miss_st1, force_request_miss_st1);
`SCOPE_ASSIGN (scope_stall_pipe, stall_bank_pipe);
`SCOPE_ASSIGN (is_mrvq_st1, is_mrvq_st1);
`SCOPE_ASSIGN (miss_st1, miss_st1);
`SCOPE_ASSIGN (dirty_st1, dirty_st1);
`SCOPE_ASSIGN (force_miss_st1, force_request_miss_st1);
`SCOPE_ASSIGN (stall_pipe, stall_bank_pipe);
`SCOPE_ASSIGN (scope_addr_st0, `LINE_TO_BYTE_ADDR(qual_addr_st0, BANK_ID));
`SCOPE_ASSIGN (scope_addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
`SCOPE_ASSIGN (scope_addr_st2, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID));
`SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(qual_addr_st0, BANK_ID));
`SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
`SCOPE_ASSIGN (addr_st2, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID));
endmodule