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RAM blocks inference fixes

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This commit is contained in:
Blaise Tine
2020-11-30 14:02:47 -08:00
parent 5758ef9ebf
commit 97739e9dcf
27 changed files with 218 additions and 189 deletions
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55
hw/rtl/libs/VX_cam_buffer.v
View File

@@ -3,8 +3,6 @@
module VX_cam_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter RPORTS = 1,
parameter CPORTS = 1,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
@@ -12,13 +10,12 @@ module VX_cam_buffer #(
output wire [ADDRW-1:0] write_addr,
input wire [DATAW-1:0] write_data,
input wire acquire_slot,
input wire [RPORTS-1:0][ADDRW-1:0] read_addr,
output wire [RPORTS-1:0][DATAW-1:0] read_data,
input wire [CPORTS-1:0][ADDRW-1:0] release_addr,
input wire [CPORTS-1:0] release_slot,
input wire [ADDRW-1:0] read_addr,
output wire [DATAW-1:0] read_data,
input wire [ADDRW-1:0] release_addr,
input wire release_slot,
output wire full
);
reg [DATAW-1:0] entries [SIZE-1:0];
reg [SIZE-1:0] free_slots, free_slots_n;
reg [ADDRW-1:0] write_addr_r;
reg full_r;
@@ -36,13 +33,12 @@ module VX_cam_buffer #(
always @(*) begin
free_slots_n = free_slots;
for (integer i = 0; i < CPORTS; i++) begin
if (release_slot[i]) begin
free_slots_n[release_addr[i]] = 1;
end
if (release_slot) begin
free_slots_n[release_addr] = 1;
end
if (acquire_slot) begin
free_slots_n[write_addr_r] = 0;
assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
free_slots_n[write_addr_r] = 0;
end
end
@@ -52,28 +48,33 @@ module VX_cam_buffer #(
full_r <= 1'b0;
write_addr_r <= ADDRW'(1'b0);
end else begin
for (integer i = 0; i < CPORTS; i++) begin
if (release_slot[i]) begin
assert(0 == free_slots[release_addr[i]]) else begin
$display("%t: releasing invalid slot at port %d", $time, release_addr[i]);
end
if (release_slot) begin
assert(0 == free_slots[release_addr]) else begin
$display("%t: releasing invalid slot at port %d", $time, release_addr);
end
end
free_slots <= free_slots_n;
write_addr_r <= free_index;
full_r <= ~free_valid;
end
if (acquire_slot) begin
assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
entries[write_addr] <= write_data;
end
end
for (genvar i = 0; i < RPORTS; i++) begin
assign read_data[i] = entries[read_addr[i]];
end
end
VX_dp_ram #(
.DATAW(DATAW),
.SIZE(SIZE),
.BUFFERED(0),
.RWCHECK(0)
) req_metadata (
.clk(clk),
.waddr(write_addr),
.raddr(read_addr),
.wren(acquire_slot),
.byteen(1'b1),
.rden(1'b1),
.din(write_data),
.dout(read_data)
);
assign write_addr = write_addr_r;
assign full = full_r;

4
hw/rtl/libs/VX_divide.v
View File

@@ -73,8 +73,8 @@ module VX_divide #(
assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0];
end else begin
reg [WIDTHN-1:0] quotient_pipe [0:LATENCY-1];
reg [WIDTHD-1:0] remainder_pipe [0:LATENCY-1];
reg [WIDTHN-1:0] quotient_pipe [LATENCY-1:0];
reg [WIDTHD-1:0] remainder_pipe [LATENCY-1:0];
for (genvar i = 0; i < LATENCY; i++) begin
always @(posedge clk) begin

134
hw/rtl/libs/VX_dp_ram.v
View File

@@ -21,33 +21,40 @@ module VX_dp_ram #(
output wire [DATAW-1:0] dout
);
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
localparam DATA32W = DATAW / 32;
localparam BYTEEN32W = BYTEENW / 4;
if (FASTRAM) begin
if (BUFFERED) begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
if (BUFFERED) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
if (rden)
dout_r <= mem[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
if (rden)
dout_r <= mem[raddr];
end
end
always @(posedge clk) begin
if (rden)
dout_r <= mem[raddr];
end
assign dout = dout_r;
@@ -55,48 +62,58 @@ module VX_dp_ram #(
`UNUSED_VAR (rden)
if (RWCHECK) begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
if (RWCHECK) begin
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[raddr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
assign dout = mem[raddr];
end
assign dout = mem[raddr];
end else begin
`USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
`USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[raddr];
end else begin
`USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
end
assign dout = mem[raddr];
assign dout = mem[raddr];
end
end
end
@@ -104,79 +121,88 @@ module VX_dp_ram #(
if (BUFFERED) begin
reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
if (rden)
dout_r <= mem[raddr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
if (rden)
dout_r <= mem[raddr];
end
end
always @(posedge clk) begin
if (rden)
dout_r <= mem[raddr];
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[raddr];
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
assign dout = mem[raddr];
end
assign dout = mem[raddr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[raddr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
end
assign dout = mem[raddr];
assign dout = mem[raddr];
end
end
end
end

31
hw/rtl/libs/VX_generic_queue.v
View File

@@ -6,7 +6,7 @@ module VX_generic_queue #(
parameter BUFFERED = 0,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 1
parameter FASTRAM = 0
) (
input wire clk,
input wire reset,
@@ -117,7 +117,7 @@ module VX_generic_queue #(
.raddr(rd_ptr_a),
.wren(push),
.byteen(1'b1),
.rden(pop),
.rden(1'b1),
.din(data_in),
.dout(data_out)
);
@@ -125,11 +125,10 @@ module VX_generic_queue #(
end else begin
wire [DATAW-1:0] dout;
reg [DATAW-1:0] din_r;
reg [DATAW-1:0] dout_r;
reg [ADDRW-1:0] wr_ptr_r;
reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] rd_ptr_n_r;
reg bypass_r;
always @(posedge clk) begin
if (reset) begin
@@ -151,19 +150,11 @@ module VX_generic_queue #(
end
end
always @(posedge clk) begin
if (push && (empty_r || ((used_r == ADDRW'(1)) && pop))) begin
bypass_r <= 1;
din_r <= data_in;
end else if (pop)
bypass_r <= 0;
end
VX_dp_ram #(
.DATAW(DATAW),
.SIZE(SIZE),
.BUFFERED(1),
.RWCHECK(0),
.BUFFERED(0),
.RWCHECK(1),
.FASTRAM(FASTRAM)
) dp_ram (
.clk(clk),
@@ -171,12 +162,20 @@ module VX_generic_queue #(
.raddr(rd_ptr_n_r),
.wren(push),
.byteen(1'b1),
.rden(pop),
.rden(1'b1),
.din(data_in),
.dout(dout)
);
assign data_out = bypass_r ? din_r : dout;
always @(posedge clk) begin
if (push && (empty_r || ((used_r == ADDRW'(1)) && pop))) begin
dout_r <= data_in;
end else if (pop) begin
dout_r <= dout;
end
end
assign data_out = dout_r;
end
assign empty = empty_r;

4
hw/rtl/libs/VX_matrix_arbiter.v
View File

@@ -22,8 +22,8 @@ module VX_matrix_arbiter #(
end else begin
reg [N-1:1] state [0:N-1];
wire [N-1:0] pri [0:N-1];
reg [N-1:1] state [N-1:0];
wire [N-1:0] pri [N-1:0];
for (genvar i = 0; i < N; i++) begin
for (genvar j = 0; j < N; j++) begin

2
hw/rtl/libs/VX_multiplier.v
View File

@@ -47,7 +47,7 @@ module VX_multiplier #(
if (LATENCY == 0) begin
assign result = result_unqual;
end else begin
reg [WIDTHP-1:0] result_pipe [0:LATENCY-1];
reg [WIDTHP-1:0] result_pipe [LATENCY-1:0];
for (genvar i = 0; i < LATENCY; i++) begin
always @(posedge clk) begin

2
hw/rtl/libs/VX_rr_arbiter.v
View File

@@ -22,7 +22,7 @@ module VX_rr_arbiter #(
end else begin
reg [`CLOG2(N)-1:0] grant_table [0:N-1];
reg [`CLOG2(N)-1:0] grant_table [N-1:0];
reg [`CLOG2(N)-1:0] state;
reg [N-1:0] grant_onehot_r;