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RAM blocks inference fixes

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This commit is contained in:
Blaise Tine
2020-11-30 14:02:47 -08:00
parent 5758ef9ebf
commit 97739e9dcf
27 changed files with 218 additions and 189 deletions
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6
hw/rtl/cache/VX_bank.v vendored
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@@ -498,6 +498,7 @@ if (DRAM_ENABLE) begin
end else begin
`UNUSED_VAR (mshr_pending_hazard_unqual_st0)
`UNUSED_VAR (addr_st0)
assign {tag_st1, mem_rw_st1, mem_byteen_st1, tid_st1} = inst_meta_st1;
@@ -510,7 +511,7 @@ end else begin
assign writedata_st1= writedata_st0;
assign inst_meta_st1= inst_meta_st0;
assign snp_inv_st1 = snp_inv_st0;
assign addr_st1 = addr_st0;
assign addr_st1 = reqq_addr_st0[`LINE_SELECT_ADDR_RNG];
assign dirty_st1 = 0;
assign readtag_st1 = 0;
assign miss_st1 = 0;
@@ -782,7 +783,8 @@ end
VX_generic_queue #(
.DATAW(`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
.SIZE(CWBQ_SIZE)
.SIZE(CWBQ_SIZE),
.BUFFERED(1)
) cwb_queue (
.clk (clk),
.reset (reset),