RAM blocks inference fixes
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@@ -16,14 +16,11 @@ module VX_ipdom_stack #(
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);
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localparam STACK_SIZE = 2 ** DEPTH;
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`NO_RW_RAM_CHECK reg [WIDTH-1:0] stack_1 [0:STACK_SIZE-1];
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`NO_RW_RAM_CHECK reg [WIDTH-1:0] stack_2 [0:STACK_SIZE-1];
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reg is_part [0:STACK_SIZE-1];
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reg is_part [STACK_SIZE-1:0];
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reg [DEPTH-1:0] rd_ptr, wr_ptr;
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reg [WIDTH - 1:0] d1, d2;
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reg p;
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wire [WIDTH - 1:0] d1, d2;
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always @(posedge clk) begin
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if (reset) begin
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@@ -38,22 +35,24 @@ module VX_ipdom_stack #(
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rd_ptr <= rd_ptr - DEPTH'(is_part[rd_ptr]);
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end
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end
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end
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always @(posedge clk) begin
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if (push) begin
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stack_1[wr_ptr] <= q1;
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end
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end
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assign d1 = stack_1[rd_ptr];
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always @(posedge clk) begin
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if (push) begin
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stack_2[wr_ptr] <= q2;
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end
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end
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assign d2 = stack_2[rd_ptr];
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end
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VX_dp_ram #(
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.DATAW(WIDTH * 2),
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.SIZE(STACK_SIZE),
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.BUFFERED(0),
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.RWCHECK(0)
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) store (
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.clk(clk),
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.waddr(wr_ptr),
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.raddr(rd_ptr),
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.wren(push),
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.byteen(1'b1),
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.rden(1'b1),
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.din({q2, q1}),
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.dout({d2, d1})
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);
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always @(posedge clk) begin
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if (push) begin
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is_part[wr_ptr] <= 0;
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@@ -61,7 +60,7 @@ module VX_ipdom_stack #(
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is_part[rd_ptr] <= 1;
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end
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end
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assign p = is_part[rd_ptr];
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wire p = is_part[rd_ptr];
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assign d = p ? d1 : d2;
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assign empty = ~(| wr_ptr);
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