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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
Blaise Tine
2020-06-28 22:28:12 -07:00
parent 7594067023 e919e452b9
commit 97668bf6f6
3 changed files with 8 additions and 7 deletions
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2
hw/rtl/VX_lsu_unit.v
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@@ -159,7 +159,7 @@ module VX_lsu_unit #(
assign mem_wb_if.data = core_rsp_data; assign mem_wb_if.data = core_rsp_data;
// Can't accept new response // Can't accept new response
assign dcache_rsp_if.core_rsp_ready = !no_slot_mem & (|mem_wb_if_p1.valid); assign dcache_rsp_if.core_rsp_ready = !(no_slot_mem & (|mem_wb_if_p1.valid));
// From LSU to WB // From LSU to WB
localparam WB_REQ_SIZE = (`NUM_THREADS) + (`NUM_THREADS * 32) + (`NW_BITS) + (5) + (2) + 32; localparam WB_REQ_SIZE = (`NUM_THREADS) + (`NUM_THREADS * 32) + (`NW_BITS) + (5) + (2) + 32;

8
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -34,7 +34,7 @@ module VX_cache_core_rsp_merge #(
assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}}; assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}};
wire [`BANK_BITS-1:0] main_bank_index; wire [`BANK_BITS-1:0] main_bank_index;
wire grant_valid;
VX_fair_arbiter #( VX_fair_arbiter #(
.N(NUM_BANKS) .N(NUM_BANKS)
) sel_bank ( ) sel_bank (
@@ -42,7 +42,7 @@ module VX_cache_core_rsp_merge #(
.reset (reset), .reset (reset),
.requests (per_bank_core_rsp_valid), .requests (per_bank_core_rsp_valid),
.grant_index (main_bank_index), .grant_index (main_bank_index),
`UNUSED_PIN (grant_valid), .grant_valid (grant_valid),
`UNUSED_PIN (grant_onehot) `UNUSED_PIN (grant_onehot)
); );
@@ -54,7 +54,7 @@ module VX_cache_core_rsp_merge #(
core_rsp_valid = 0; core_rsp_valid = 0;
core_rsp_data = 0; core_rsp_data = 0;
for (i = 0; i < NUM_BANKS; i++) begin for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i] if (grant_valid && per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin && (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin
core_rsp_valid[per_bank_core_rsp_tid[i]] = 1; core_rsp_valid[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
@@ -70,7 +70,7 @@ module VX_cache_core_rsp_merge #(
core_rsp_data = 0; core_rsp_data = 0;
core_rsp_tag = 0; core_rsp_tag = 0;
for (i = 0; i < NUM_BANKS; i++) begin for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i] if (grant_valid && per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]] && !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `BANK_BITS'(i)) && ((main_bank_index == `BANK_BITS'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin || (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin

5
hw/rtl/libs/VX_fair_arbiter.v
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@@ -25,6 +25,7 @@ module VX_fair_arbiter #(
reg [N-1:0] requests_use; reg [N-1:0] requests_use;
wire [N-1:0] update_value; wire [N-1:0] update_value;
wire [N-1:0] late_value;
wire refill; wire refill;
wire [N-1:0] refill_value; wire [N-1:0] refill_value;
@@ -60,8 +61,8 @@ module VX_fair_arbiter #(
grant_onehot_r[grant_index] = 1; grant_onehot_r[grant_index] = 1;
end end
assign grant_onehot = grant_onehot_r; assign grant_onehot = grant_onehot_r;
assign late_value = ((refill_original ^ requests) & ~refill_original);
assign update_value = (requests_use & ~grant_onehot_r) | ((refill_original ^ requests) & ~refill_original); assign update_value = (requests_use & ~grant_onehot_r) | late_value;
end end