From 970cbf066a4dba4ac50579e6971249eab844ea6e Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Fri, 3 Nov 2023 08:09:59 -0400
Subject: [PATCH] cleanup

---
 sim/simx/cluster.cpp  |  5 +----
 sim/simx/cluster.h    |  6 ------
 sim/simx/core.h       |  4 ----
 sim/simx/decode.cpp   |  9 ---------
 sim/simx/exe_unit.cpp | 14 +-------------
 sim/simx/exe_unit.h   | 37 ++++++++++++++++++-------------------
 sim/simx/types.h      |  6 ------
 7 files changed, 20 insertions(+), 61 deletions(-)

diff --git a/sim/simx/cluster.cpp b/sim/simx/cluster.cpp
index 668359a2..a129ddaa 100644
--- a/sim/simx/cluster.cpp
+++ b/sim/simx/cluster.cpp
@@ -208,10 +208,7 @@ ProcessorImpl* Cluster::processor() const {
 Cluster::PerfStats Cluster::perf_stats() const {
   Cluster::PerfStats perf;
   perf.icache = icaches_->perf_stats();
-  perf.dcache = dcaches_->perf_stats();    
-  perf.tcache = tcaches_->perf_stats();
-  perf.ocache = ocaches_->perf_stats();
-  perf.rcache = rcaches_->perf_stats();
+  perf.dcache = dcaches_->perf_stats();
   perf.l2cache = l2cache_->perf_stats();
 
   for (auto sharedmem : sharedmems_) {
diff --git a/sim/simx/cluster.h b/sim/simx/cluster.h
index 84cf280e..f91241e9 100644
--- a/sim/simx/cluster.h
+++ b/sim/simx/cluster.h
@@ -32,18 +32,12 @@ public:
     CacheSim::PerfStats   dcache;
     SharedMem::PerfStats  sharedmem;
     CacheSim::PerfStats   l2cache;
-    CacheSim::PerfStats   tcache;
-    CacheSim::PerfStats   ocache;
-    CacheSim::PerfStats   rcache;
 
     PerfStats& operator+=(const PerfStats& rhs) {
       this->icache      += rhs.icache;
       this->dcache      += rhs.dcache;
       this->sharedmem   += rhs.sharedmem;
       this->l2cache     += rhs.l2cache;
-      this->tcache      += rhs.tcache;
-      this->ocache      += rhs.ocache;
-      this->rcache      += rhs.rcache;
       return *this;
     }
   };
diff --git a/sim/simx/core.h b/sim/simx/core.h
index 680cecf0..ed06574d 100644
--- a/sim/simx/core.h
+++ b/sim/simx/core.h
@@ -197,10 +197,6 @@ private:
   friend class AluUnit;
   friend class FpuUnit;
   friend class SfuUnit;
-  friend class TexUnit;
-  friend class RasterAgent;
-  friend class RopAgent;
-  friend class TexAgent;
 };
 
 } // namespace vortex
diff --git a/sim/simx/decode.cpp b/sim/simx/decode.cpp
index ea1dabb3..754ae516 100644
--- a/sim/simx/decode.cpp
+++ b/sim/simx/decode.cpp
@@ -553,15 +553,6 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
           std::abort();
         }
         break;
-      case 1:
-        switch (func3) {
-        case 0: // RASTER
-          instr->setDestReg(rd, RegType::Integer);
-          break;
-        default:
-          std::abort();
-        }
-        break;
       default:
         std::abort();
       }
diff --git a/sim/simx/exe_unit.cpp b/sim/simx/exe_unit.cpp
index 16ac6e72..2f3e79e3 100644
--- a/sim/simx/exe_unit.cpp
+++ b/sim/simx/exe_unit.cpp
@@ -271,22 +271,10 @@ void LsuUnit::tick() {
 
 SfuUnit::SfuUnit(const SimContext& ctx, Core* core) 
     : ExeUnit(ctx, core, "SFU")
+    , input_idx_(0)
 {}
     
 void SfuUnit::tick() {
-    // handle pending responses
-    for (auto pending_rsp : pending_rsps_) {
-        if (pending_rsp->empty())
-            continue;
-        auto trace = pending_rsp->front();
-        if (trace->cid != core_->id())
-            continue;
-        int iw = trace->wid % ISSUE_WIDTH;
-        auto& output = Outputs.at(iw);
-        output.send(trace, 1);
-        pending_rsp->pop();
-    }
-
     // check input queue
     for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
         int iw = (input_idx_ + i) % ISSUE_WIDTH;        
diff --git a/sim/simx/exe_unit.h b/sim/simx/exe_unit.h
index dded840c..5554d9a0 100644
--- a/sim/simx/exe_unit.h
+++ b/sim/simx/exe_unit.h
@@ -45,6 +45,24 @@ protected:
 
 ///////////////////////////////////////////////////////////////////////////////
 
+class AluUnit : public ExeUnit {
+public:
+    AluUnit(const SimContext& ctx, Core*);
+    
+    void tick();
+};
+
+///////////////////////////////////////////////////////////////////////////////
+
+class FpuUnit : public ExeUnit {
+public:
+    FpuUnit(const SimContext& ctx, Core*);
+    
+    void tick();
+};
+
+///////////////////////////////////////////////////////////////////////////////
+
 class LsuUnit : public ExeUnit {
 public:
     LsuUnit(const SimContext& ctx, Core*);
@@ -68,24 +86,6 @@ private:
 
 ///////////////////////////////////////////////////////////////////////////////
 
-class AluUnit : public ExeUnit {
-public:
-    AluUnit(const SimContext& ctx, Core*);
-    
-    void tick();
-};
-
-///////////////////////////////////////////////////////////////////////////////
-
-class FpuUnit : public ExeUnit {
-public:
-    FpuUnit(const SimContext& ctx, Core*);
-    
-    void tick();
-};
-
-///////////////////////////////////////////////////////////////////////////////
-
 class SfuUnit : public ExeUnit {
 public:
     SfuUnit(const SimContext& ctx, Core*);
@@ -93,7 +93,6 @@ public:
     void tick();
 
 private:
-  std::vector<SimPort<pipeline_trace_t*>*> pending_rsps_;
   uint32_t input_idx_;
 };
 
diff --git a/sim/simx/types.h b/sim/simx/types.h
index 2612d546..88b3ce0e 100644
--- a/sim/simx/types.h
+++ b/sim/simx/types.h
@@ -190,9 +190,6 @@ enum class SfuType {
   CSRRW,
   CSRRS,
   CSRRC,
-  TEX,
-  RASTER,
-  ROP,    
   CMOV  
 };
 
@@ -207,9 +204,6 @@ inline std::ostream &operator<<(std::ostream &os, const SfuType& type) {
   case SfuType::CSRRW:  os << "CSRRW"; break;
   case SfuType::CSRRS:  os << "CSRRS"; break;
   case SfuType::CSRRC:  os << "CSRRC"; break;
-  case SfuType::TEX:    os << "TEX"; break;
-  case SfuType::RASTER: os << "RASTER"; break;
-  case SfuType::ROP:    os << "ROP"; break;
   case SfuType::CMOV:   os << "CMOV"; break;
   }
   return os;