From 97041e8e82f763c10b9459bc0c8e67287cfd69e7 Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@hotmail.com>
Date: Mon, 22 Mar 2021 10:41:50 -0400
Subject: [PATCH] tex_unit code refactoring

---
 hw/rtl/tex_unit/VX_bilerp.v      | 71 --------------------------------
 hw/rtl/tex_unit/VX_lerp.v        | 18 --------
 hw/rtl/tex_unit/VX_tex_define.vh | 12 ++----
 hw/rtl/tex_unit/VX_tex_format.v  | 57 ++-----------------------
 hw/rtl/tex_unit/VX_tex_sampler.v |  5 ---
 5 files changed, 8 insertions(+), 155 deletions(-)
 delete mode 100644 hw/rtl/tex_unit/VX_bilerp.v
 delete mode 100644 hw/rtl/tex_unit/VX_lerp.v

diff --git a/hw/rtl/tex_unit/VX_bilerp.v b/hw/rtl/tex_unit/VX_bilerp.v
deleted file mode 100644
index 5493bd9a..00000000
--- a/hw/rtl/tex_unit/VX_bilerp.v
+++ /dev/null
@@ -1,71 +0,0 @@
-`include "VX_tex_define.vh"
-
-module VX_bilerp #(
-    parameter CORE_ID = 0
-) (
-    input wire [`BLEND_FRAC_64-1:0]   blendU, //blendU
-    input wire [`BLEND_FRAC_64-1:0]   blendV,  //blendV
-
-    input wire [3:0][63:0]            texels,
-    input wire [`TEX_FORMAT_BITS-1:0] color_enable,
-
-    output wire [31:0]                sampled_data
-);  
-    `UNUSED_PARAM (CORE_ID)
-    `UNUSED_VAR(color_enable)
-
-    wire [63:0] UL_lerp;
-    wire [63:0] UH_lerp;
-    wire [63:0] V_lerp;
-    reg [31:0] sampled_r;
-
-    VX_lerp_64 #(
-    ) UL_lerp (
-    .blend(blendU), 
-    .in_texels({texels[1], texels[0]}),
-
-    .lerp_texel(UL_lerp)
-    );  
-
-    VX_lerp_64 #(
-    ) UH_lerp (
-    .blend(blendU), 
-    .in_texels({texels[3], texels[2]}),
-
-    .lerp_texel(UH_lerp)
-    );  
-
-    VX_lerp_64 #(
-    ) V_lerp (
-    .blend(blendV), 
-    .in_texels({UH_lerp, UL_lerp}),
-
-    .lerp_texel(V_lerp)
-    );  
-
-    always @(*) begin
-        if(color_enable[3]==1) //R
-            sampled_r[31:24] = V_lerp[55:48];
-        else
-            sampled_r[31:24] = {`TEX_COLOR_BITS{1'b0}};
-
-        if(color_enable[2]==1) //G
-            sampled_r[23:16] = V_lerp[39:32];
-        else
-            sampled_r[23:16] = {`TEX_COLOR_BITS{1'b0}};
-
-        if(color_enable[1]==1) //B
-            sampled_r[15:8] = V_lerp[23:16];
-        else
-            sampled_r[15:8] = {`TEX_COLOR_BITS{1'b0}};
-
-        if(color_enable[0]==1) //A
-            sampled_r[7:0] = V_lerp[7:0];
-        else
-            sampled_r[7:0] = {`TEX_COLOR_BITS{1'b1}};
-    end
-
-
-    assign sampled_data = sampled_r;
-
-endmodule
\ No newline at end of file
diff --git a/hw/rtl/tex_unit/VX_lerp.v b/hw/rtl/tex_unit/VX_lerp.v
deleted file mode 100644
index 40e0baf8..00000000
--- a/hw/rtl/tex_unit/VX_lerp.v
+++ /dev/null
@@ -1,18 +0,0 @@
-`include "VX_tex_define.vh"
-
-module VX_lerp_64 #(
-) (
-    input wire [`BLEND_FRAC_64-1:0]   blend, 
-    input wire [1:0][63:0]            in_texels,
-
-    output wire [63:0]                lerp_texel
-);  
-
-    wire [63:0] lerp_i1;
-    wire [63:0] lerp_i2; // >> BLEND_FRAC_64 / >> 8
-
-    assign lerp_i1 = (in_texels[0] - in_texels[1]) * blend;
-    assign lerp_i2 = in_texels[1] + {8'h00,lerp_i1[63:56], 8'h00,lerp_i1[47:40], 8'h00,lerp_i1[31:24], 8'h00,lerp_i1[15:8]};
-    assign lerp_texel = lerp_i2 & 64'h00ff00ff00ff00ff;
-
-endmodule
\ No newline at end of file
diff --git a/hw/rtl/tex_unit/VX_tex_define.vh b/hw/rtl/tex_unit/VX_tex_define.vh
index ef305c76..f73413e0 100644
--- a/hw/rtl/tex_unit/VX_tex_define.vh
+++ b/hw/rtl/tex_unit/VX_tex_define.vh
@@ -12,6 +12,7 @@
 `define CLAMP(x,lo,hi)  ((x < lo) ? lo : ((x > hi) ? hi : x))
 
 `define BLEND_FRAC_64    8
+
 `define LERP_64(x1,x2,frac) ((x2 + (((x1 - x2) * frac) >> `BLEND_FRAC_64)) & 64'h00ff00ff00ff00ff)
 
 `define TEX_ADDR_BITS    32
@@ -31,13 +32,8 @@
 
 `define TEX_COLOR_BITS    8
 
-`define R5G6B5            `TEX_FORMAT_BITS'h1
-`define R8G8B8            `TEX_FORMAT_BITS'h2
-`define R8G8B8A8          `TEX_FORMAT_BITS'h3
-
-`define RBEGIN            24
-`define GBEGIN            16
-`define BBEGIN            8
-`define ABEGIN            0
+`define TEX_FORMAT_R5G6B5       `TEX_FORMAT_BITS'(1)
+`define TEX_FORMAT_R8G8B8       `TEX_FORMAT_BITS'(2)
+`define TEX_FORMAT_R8G8B8A8     `TEX_FORMAT_BITS'(3)
 
 `endif
\ No newline at end of file
diff --git a/hw/rtl/tex_unit/VX_tex_format.v b/hw/rtl/tex_unit/VX_tex_format.v
index 6279c6b7..a64a829b 100644
--- a/hw/rtl/tex_unit/VX_tex_format.v
+++ b/hw/rtl/tex_unit/VX_tex_format.v
@@ -18,7 +18,7 @@ module VX_tex_format #(
     always @(*) begin
         for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
             case (format)
-                `R5G6B5: begin
+                `TEX_FORMAT_R5G6B5: begin
                     formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][15:11]);
                     formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][10:5]);
                     formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][4:0]);
@@ -26,7 +26,7 @@ module VX_tex_format #(
                     if (i == 0)
                         color_enable_r = 4'b1110;
                 end
-                `R8G8B8: begin
+                `TEX_FORMAT_R8G8B8: begin
                     formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
                     formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
                     formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
@@ -34,7 +34,7 @@ module VX_tex_format #(
                     if (i == 0)
                         color_enable_r = 4'b1110;
                 end
-                default: begin // `R8G8B8A8:
+                default: begin // `TEX_FORMAT_R8G8B8A8:
                     formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][31:24]);
                     formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
                     formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
@@ -46,56 +46,7 @@ module VX_tex_format #(
         end
     end
 
-    assign color_enable = color_enable_r;
+    assign color_enable    = color_enable_r;
     assign formatted_texel = formatted_texel_r & 64'h00ff00ff00ff00ff;
 
 endmodule
-
-// module VX_tex_format #(
-//     parameter CORE_ID = 0
-// ) (
-//     input wire [`TEX_FORMAT_BITS-1:0]   format,
-//     input wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
-
-//     input wire [`TEX_COLOR_BITS-1:0]    R,
-//     input wire [`TEX_COLOR_BITS-1:0]    G,
-//     input wire [`TEX_COLOR_BITS-1:0]    B,
-//     input wire [`TEX_COLOR_BITS-1:0]    A,
-
-//     output wire [31:0]                  texel_sampled
-// );  
-//     `UNUSED_PARAM (CORE_ID)
-//     `UNUSED_VAR(color_enable)
-
-//     reg [63:0]  sampled_r;
-
-//     always @(*) begin
-//         case (format)
-//             `R5G6B5: begin
-//                 sampled_r[31:16] = 'd0;
-//                 sampled_r[15:11] = R[4:0];
-//                 sampled_r[10:5] = G[5:0];
-//                 sampled_r[4:0] = B[4:0];
-//             end
-
-//             `R8G8B8: begin
-//                 sampled_r[31:24] = 'd0;
-//                 sampled_r[23:16] = R;
-//                 sampled_r[15:8]  = G;
-//                 sampled_r[7:0]   = B;
-//             end
-            
-//             default: begin // `R8G8B8A8:
-//                 sampled_r[31:24] = R;
-//                 sampled_r[23:16] = R;
-//                 sampled_r[15:8]  = G;
-//                 sampled_r[7:0]   = A;
-//             end
-//         endcase
-//     end
-
-//     assign texel_sampled = sampled_r;
-
-// endmodule
-
-
diff --git a/hw/rtl/tex_unit/VX_tex_sampler.v b/hw/rtl/tex_unit/VX_tex_sampler.v
index eee2ff5f..51c42543 100644
--- a/hw/rtl/tex_unit/VX_tex_sampler.v
+++ b/hw/rtl/tex_unit/VX_tex_sampler.v
@@ -79,7 +79,6 @@ module VX_tex_sampler #(
             );    
 
         end
-
     end
 
     assign stall_out = ~rsp_ready;
@@ -96,8 +95,4 @@ module VX_tex_sampler #(
         .data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
     );
 
-
-
-
-
 endmodule
\ No newline at end of file