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fpga build refactoring

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This commit is contained in:
Blaise Tine
2021-04-29 06:17:28 -07:00
parent 2216a3059d
commit 95f057bc2e
16 changed files with 185 additions and 208 deletions
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194
hw/syn/opae/Makefile
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@@ -1,11 +1,14 @@
ASE_BUILD_DIR ?= build_ase
FPGA_BUILD_DIR ?= build_fpga
DEVICE_FAMILY ?= arria10
RTL_DIR=../../rtl
ifdef $(shell [[ '$(FPGA_CLASS)' =~ 'fpga-pac-s10' ]] && echo matched)
DEVICE_FAMILY ?= stratix10
else
DEVICE_FAMILY ?= arria10
ifeq ($(DEVICE_FAMILY),arria10)
CFLAGS += -DMEM_BLOCK_SIZE=64
endif
ifeq ($(DEVICE_FAMILY),stratix10)
CFLAGS += -DMEM_BLOCK_SIZE=16
endif
ifeq ($(shell which qsub-synth),)
@@ -14,22 +17,106 @@ else
RUN_SYNTH=qsub-synth
endif
# control RTL debug print states
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK
DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR
DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG
DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA
DBG_PRINT_FLAGS += -DDBG_PRINT_MEM
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_PRINT_FLAGS += -DDBG_PRINT_AVS
DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CACHE_REQ_INFO
CONFIG1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG8 := -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG32 := -DNUM_CLUSTERS=4 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)
RTL_INCLUDE = -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/afu
CFLAGS += $(RTL_INCLUDE)
# Debugigng
ifdef DEBUG
CFLAGS += $(DBG_FLAGS)
else
CFLAGS += -DNDEBUG
endif
# Enable scope analyzer
ifdef SCOPE
CFLAGS += -DSCOPE
endif
# Enable perf counters
ifdef PERF
CFLAGS += -DPERF_ENABLE
endif
all: ase-1c
gen-sources:
./gen_sources.sh $(DEVICE_FAMILY) > sources.txt
$(ASE_BUILD_DIR)_1c/Makefile:
afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_1c
ase-1c: gen-sources setup-ase-1c
make -C $(ASE_BUILD_DIR)_1c
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_1c/work
$(ASE_BUILD_DIR)_2c/Makefile:
afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_2c
ase-2c: gen-sources setup-ase-2c
make -C $(ASE_BUILD_DIR)_2c
cp $(RTL_DIR)/fp_cores/altera/arria$(DEVICE_FAMILY)10/*.hex $(ASE_BUILD_DIR)_2c/work
$(ASE_BUILD_DIR)_4c/Makefile:
afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_4c
ase-4c: gen-sources setup-ase-4c
make -C $(ASE_BUILD_DIR)_4c
cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_4c/work
$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_1c
$(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_2c
$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_4c
$(FPGA_BUILD_DIR)_8c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_8c
$(FPGA_BUILD_DIR)_16c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_16c
$(FPGA_BUILD_DIR)_32c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_32c
$(FPGA_BUILD_DIR)_64c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_64c
gen-sources-1c:
./gen_sources.sh $(CFLAGS) $(CONFIG1) > sources.txt
gen-sources-2c:
./gen_sources.sh $(CFLAGS) $(CONFIG2) > sources.txt
gen-sources-4c:
./gen_sources.sh $(CFLAGS) $(CONFIG4) > sources.txt
gen-sources-8c:
./gen_sources.sh $(CFLAGS) $(CONFIG8) > sources.txt
gen-sources-16c:
./gen_sources.sh $(CFLAGS) $(CONFIG16) > sources.txt
gen-sources-32c:
./gen_sources.sh $(CFLAGS) $(CONFIG32) > sources.txt
gen-sources-64c:
./gen_sources.sh $(CFLAGS) $(CONFIG64) > sources.txt
# setup
setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
@@ -37,36 +124,6 @@ setup-ase-2c: $(ASE_BUILD_DIR)_2c/Makefile
setup-ase-4c: $(ASE_BUILD_DIR)_4c/Makefile
$(ASE_BUILD_DIR)_1c/Makefile:
afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c
$(ASE_BUILD_DIR)_2c/Makefile:
afu_sim_setup -s sources_2c.txt $(ASE_BUILD_DIR)_2c
$(ASE_BUILD_DIR)_4c/Makefile:
afu_sim_setup -s sources_4c.txt $(ASE_BUILD_DIR)_4c
fpga-1c: gen-sources setup-fpga-1c
cd $(FPGA_BUILD_DIR)_1c && $(RUN_SYNTH)
fpga-2c: gen-sources setup-fpga-2c
cd $(FPGA_BUILD_DIR)_2c && $(RUN_SYNTH)
fpga-4c: gen-sources setup-fpga-4c
cd $(FPGA_BUILD_DIR)_4c && $(RUN_SYNTH)
fpga-8c: gen-sources setup-fpga-8c
cd $(FPGA_BUILD_DIR)_8c && $(RUN_SYNTH)
fpga-16c: gen-sources setup-fpga-16c
cd $(FPGA_BUILD_DIR)_16c && $(RUN_SYNTH)
fpga-32c: gen-sources setup-fpga-32c
cd $(FPGA_BUILD_DIR)_32c && $(RUN_SYNTH)
fpga-64c: gen-sources setup-fpga-64c
cd $(FPGA_BUILD_DIR)_64c && $(RUN_SYNTH)
setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
setup-fpga-2c: $(FPGA_BUILD_DIR)_2c/build/dcp.qpf
@@ -81,35 +138,42 @@ setup-fpga-32c: $(FPGA_BUILD_DIR)_32c/build/dcp.qpf
setup-fpga-64c: $(FPGA_BUILD_DIR)_64c/build/dcp.qpf
$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c
# build
$(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
afu_synth_setup -s sources_2c.txt $(FPGA_BUILD_DIR)_2c
ase-1c: gen-sources-1c setup-ase-1c
make -C $(ASE_BUILD_DIR)_1c
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_1c/work
$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
afu_synth_setup -s sources_4c.txt $(FPGA_BUILD_DIR)_4c
ase-2c: gen-sources-2c setup-ase-2c
make -C $(ASE_BUILD_DIR)_2c
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_2c/work
$(FPGA_BUILD_DIR)_8c/build/dcp.qpf:
afu_synth_setup -s sources_8c.txt $(FPGA_BUILD_DIR)_8c
ase-4c: gen-sources-4c setup-ase-4c
make -C $(ASE_BUILD_DIR)_4c
cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_4c/work
$(FPGA_BUILD_DIR)_16c/build/dcp.qpf:
afu_synth_setup -s sources_16c.txt $(FPGA_BUILD_DIR)_16c
fpga-1c: gen-sources-1c setup-fpga-1c
cd $(FPGA_BUILD_DIR)_1c && $(RUN_SYNTH)
$(FPGA_BUILD_DIR)_32c/build/dcp.qpf:
afu_synth_setup -s sources_32c.txt $(FPGA_BUILD_DIR)_32c
fpga-2c: gen-sources-2c setup-fpga-2c
cd $(FPGA_BUILD_DIR)_2c && $(RUN_SYNTH)
$(FPGA_BUILD_DIR)_64c/build/dcp.qpf:
afu_synth_setup -s sources_64c.txt $(FPGA_BUILD_DIR)_64c
fpga-4c: gen-sources-4c setup-fpga-4c
cd $(FPGA_BUILD_DIR)_4c && $(RUN_SYNTH)
run-ase-1c:
cd $(ASE_BUILD_DIR)_1c && make sim
fpga-8c: gen-sources-8c setup-fpga-8c
cd $(FPGA_BUILD_DIR)_8c && $(RUN_SYNTH)
run-ase-2c:
cd $(ASE_BUILD_DIR)_2c && make sim
fpga-16c: gen-sources-16c setup-fpga-16c
cd $(FPGA_BUILD_DIR)_16c && $(RUN_SYNTH)
run-ase-4c:
cd $(ASE_BUILD_DIR)_4c && make sim
fpga-32c: gen-sources-32c setup-fpga-32c
cd $(FPGA_BUILD_DIR)_32c && $(RUN_SYNTH)
fpga-64c: gen-sources-64c setup-fpga-64c
cd $(FPGA_BUILD_DIR)_64c && $(RUN_SYNTH)
# cleanup
clean-ase-1c:
rm -rf $(ASE_BUILD_DIR)_1c sources.txt