fpga build refactoring

2021-04-29 06:17:28 -07:00
parent 2216a3059d
commit 95f057bc2e
16 changed files with 185 additions and 208 deletions
--- a/hw/simulate/Makefile
+++ b/hw/simulate/Makefile
@@ -49,8 +49,9 @@ VL_FLAGS += verilator.vlt
 VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE)
 VL_FLAGS += --cc Vortex.v --top-module $(TOP)

-# Use FPNEW PFU core
-VL_FLAGS += -DFPU_FPNEW
+# FPU backend
+FPU_CORE ?= FPU_DPI
+VL_FLAGS += -D$(FPU_CORE)

 DBG_FLAGS += -DVCD_OUTPUT