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minor update

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This commit is contained in:
Blaise Tine
2021-07-01 02:59:44 -07:00
parent ce66ef58a8
commit 93fee18d59
9 changed files with 109 additions and 111 deletions
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173
hw/rtl/VX_decode.v
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@@ -2,17 +2,15 @@
`include "VX_print_instr.vh"
`ifdef EXT_F_ENABLE
`define SET_REG(d,f,s) \
d = {f, s}
`define USED_REG(d,f,s) \
`SET_REG(d,f,s); \
used_regs[{f, s}] = 1
`define USED_IREG(r) \
used_regs[{1'b0, r}] = 1
`define USED_FREG(r) \
r``_r[5] = 1; \
used_regs[{1'b1, r}] = 1
`else
`define SET_REG(d,f,s) \
d = s
`define USED_REG(d,f,s) \
`SET_REG(d,f,s); \
used_regs[s] = 1
`define USED_IREG(r) \
used_regs[r] = 1
`endif
module VX_decode #(
@@ -50,10 +48,8 @@ module VX_decode #(
wire [4:0] rd = instr[11:7];
wire [4:0] rs1 = instr[19:15];
wire [4:0] rs2 = instr[24:20];
`ifdef EXT_F_ENABLE
wire [4:0] rs2 = instr[24:20];
wire [4:0] rs3 = instr[31:27];
`endif
wire [19:0] upper_imm = {func7, rs2, rs1, func3};
wire [11:0] alu_imm = (func3[0] && ~func3[1]) ? {{7{1'b0}}, rs2} : u_12;
@@ -64,14 +60,14 @@ module VX_decode #(
ex_type = 0;
op_type = 'x;
op_mod = 'x;
rd_r = 'x;
rs1_r = 'x;
rs2_r = 'x;
rs3_r = 'x;
op_mod = 0;
rd_r = `NR_BITS'(rd);
rs1_r = `NR_BITS'(rs1);
rs2_r = `NR_BITS'(rs2);
rs3_r = `NR_BITS'(rs3);
imm = 'x;
use_imm = 'x;
use_PC = 'x;
use_imm = 0;
use_PC = 0;
use_rd = 0;
is_join = 0;
is_wstall = 0;
@@ -91,13 +87,11 @@ module VX_decode #(
3'h7: op_type = `OP_BITS'(`ALU_AND);
default:;
endcase
op_mod = 0;
use_rd = 1;
use_imm = 1;
use_PC = 0;
imm = {{20{alu_imm[11]}}, alu_imm};
`USED_REG (rd_r, 1'b0, rd);
`USED_REG (rs1_r, 1'b0, rs1);
`USED_IREG (rd);
`USED_IREG (rs1);
end
`INST_R: begin
ex_type = `EX_ALU;
@@ -129,35 +123,29 @@ module VX_decode #(
3'h7: op_type = `OP_BITS'(`ALU_AND);
default:;
endcase
op_mod = 0;
end
use_rd = 1;
use_imm = 0;
use_PC = 0;
`USED_REG (rd_r, 1'b0, rd);
`USED_REG (rs1_r, 1'b0, rs1);
`USED_REG (rs2_r, 1'b0, rs2);
use_rd = 1;
`USED_IREG (rd);
`USED_IREG (rs1);
`USED_IREG (rs2);
end
`INST_LUI: begin
ex_type = `EX_ALU;
op_type = `OP_BITS'(`ALU_LUI);
op_mod = 0;
use_rd = 1;
use_imm = 1;
use_PC = 0;
imm = {upper_imm, 12'(0)};
`USED_REG (rd_r, 1'b0, rd);
`USED_REG (rs1_r, 1'b0, 5'b0);
`USED_IREG (rd);
rs1_r = 0;
end
`INST_AUIPC: begin
ex_type = `EX_ALU;
op_type = `OP_BITS'(`ALU_AUIPC);
op_mod = 0;
use_rd = 1;
use_imm = 1;
use_PC = 1;
imm = {upper_imm, 12'(0)};
`USED_REG (rd_r, 1'b0, rd);
`USED_IREG (rd);
end
`INST_JAL: begin
ex_type = `EX_ALU;
@@ -168,7 +156,7 @@ module VX_decode #(
use_PC = 1;
is_wstall = 1;
imm = {{11{jal_imm[20]}}, jal_imm};
`USED_REG (rd_r, 1'b0, rd);
`USED_IREG (rd);
end
`INST_JALR: begin
ex_type = `EX_ALU;
@@ -176,11 +164,10 @@ module VX_decode #(
op_mod = 1;
use_rd = 1;
use_imm = 1;
use_PC = 0;
is_wstall = 1;
imm = {{20{jalr_imm[11]}}, jalr_imm};
`USED_REG (rd_r, 1'b0, rd);
`USED_REG (rs1_r, 1'b0, rs1);
`USED_IREG (rd);
`USED_IREG (rs1);
end
`INST_B: begin
ex_type = `EX_ALU;
@@ -198,8 +185,8 @@ module VX_decode #(
use_PC = 1;
is_wstall = 1;
imm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
`USED_REG (rs1_r, 1'b0, rs1);
`USED_REG (rs2_r, 1'b0, rs2);
`USED_IREG (rs1);
`USED_IREG (rs2);
end
`INST_F: begin
ex_type = `EX_LSU;
@@ -212,11 +199,11 @@ module VX_decode #(
use_rd = 1;
use_imm = func3[2];
imm = 32'(u_12); // addr
`USED_REG (rd_r, 1'b0, rd);
`USED_IREG (rd);
if (func3[2]) begin
`SET_REG(rs1_r, 1'b0, rs1); // imm
rs1_r = `NR_BITS'(rs1); // imm
end else begin
`USED_REG (rs1_r, 1'b0, rs1);
`USED_IREG (rs1);
end
end else begin
ex_type = `EX_ALU;
@@ -233,7 +220,7 @@ module VX_decode #(
use_imm = 1;
use_PC = 1;
imm = 32'd4;
`USED_REG (rd_r, 1'b0, rd);
`USED_IREG (rd);
end
end
`ifdef EXT_F_ENABLE
@@ -242,11 +229,15 @@ module VX_decode #(
`INST_L: begin
ex_type = `EX_LSU;
op_type = `OP_BITS'({1'b0, func3});
op_mod = 0;
use_rd = 1;
imm = {{20{u_12[11]}}, u_12};
`USED_REG (rd_r, opcode[2], rd);
`USED_REG (rs1_r, 1'b0, rs1);
`ifdef EXT_F_ENABLE
if (opcode[2]) begin
`USED_FREG (rd);
end else
`endif
`USED_IREG (rd);
`USED_IREG (rs1);
end
`ifdef EXT_F_ENABLE
`INST_FS,
@@ -254,10 +245,14 @@ module VX_decode #(
`INST_S: begin
ex_type = `EX_LSU;
op_type = `OP_BITS'({1'b1, func3});
op_mod = 0;
imm = {{20{func7[6]}}, func7, rd};
`USED_REG (rs1_r, 1'b0, rs1);
`USED_REG (rs2_r, opcode[2], rs2);
`USED_IREG (rs1);
`ifdef EXT_F_ENABLE
if (opcode[2]) begin
`USED_FREG (rs2);
end else
`endif
`USED_IREG (rs2);
end
`ifdef EXT_F_ENABLE
`INST_FMADD,
@@ -268,61 +263,61 @@ module VX_decode #(
op_type = `OP_BITS'(opcode[3:0]);
op_mod = func3;
use_rd = 1;
`USED_REG (rd_r, 1'b1, rd);
`USED_REG (rs1_r, 1'b1, rs1);
`USED_REG (rs2_r, 1'b1, rs2);
`USED_REG (rs3_r, 1'b1, rs3);
`USED_FREG (rd);
`USED_FREG (rs1);
`USED_FREG (rs2);
`USED_FREG (rs3);
end
`INST_FCI: begin
ex_type = `EX_FPU;
op_mod = func3;
use_rd = 1;
case (func7)
7'h00, // FADD
7'h04, // FSUB
7'h08, // FMUL
7'h00, // FADD
7'h04, // FSUB
7'h08, // FMUL
7'h0C: begin // FDIV
op_type = `OP_BITS'(func7[3:0]);
`USED_REG (rd_r, 1'b1, rd);
`USED_REG (rs1_r, 1'b1, rs1);
`USED_REG (rs2_r, 1'b1, rs2);
`USED_FREG (rd);
`USED_FREG (rs1);
`USED_FREG (rs2);
end
7'h2C: begin
op_type = `OP_BITS'(`FPU_SQRT);
`USED_REG (rd_r, 1'b1, rd);
`USED_REG (rs1_r, 1'b1, rs1);
`USED_FREG (rd);
`USED_FREG (rs1);
end
7'h50: begin
op_type = `OP_BITS'(`FPU_CMP);
`USED_REG (rd_r, 1'b0, rd);
`USED_REG (rs1_r, 1'b1, rs1);
`USED_REG (rs2_r, 1'b1, rs2);
`USED_IREG (rd);
`USED_FREG (rs1);
`USED_FREG (rs2);
end
7'h60: begin
op_type = (instr[20]) ? `OP_BITS'(`FPU_CVTWUS) : `OP_BITS'(`FPU_CVTWS);
`USED_REG (rd_r, 1'b0, rd);
`USED_REG (rs1_r, 1'b1, rs1);
`USED_IREG (rd);
`USED_FREG (rs1);
end
7'h68: begin
op_type = (instr[20]) ? `OP_BITS'(`FPU_CVTSWU) : `OP_BITS'(`FPU_CVTSW);
`USED_REG (rd_r, 1'b1, rd);
`USED_REG (rs1_r, 1'b0, rs1);
`USED_FREG (rd);
`USED_IREG (rs1);
end
7'h10: begin
// FSGNJ=0, FSGNJN=1, FSGNJX=2
op_type = `OP_BITS'(`FPU_MISC);
op_mod = {1'b0, func3[1:0]};
`USED_REG (rd_r, 1'b1, rd);
`USED_REG (rs1_r, 1'b1, rs1);
`USED_REG (rs2_r, 1'b1, rs2);
`USED_FREG (rd);
`USED_FREG (rs1);
`USED_FREG (rs2);
end
7'h14: begin
// FMIN=3, FMAX=4
op_type = `OP_BITS'(`FPU_MISC);
op_mod = func3[0] ? 4 : 3;
`USED_REG (rd_r, 1'b1, rd);
`USED_REG (rs1_r, 1'b1, rs1);
`USED_REG (rs2_r, 1'b1, rs2);
`USED_FREG (rd);
`USED_FREG (rs1);
`USED_FREG (rs2);
end
7'h70: begin
if (func3[0]) begin
@@ -333,15 +328,15 @@ module VX_decode #(
op_type = `OP_BITS'(`FPU_MISC);
op_mod = 5;
end
`USED_REG (rd_r, 1'b0, rd);
`USED_REG (rs1_r, 1'b1, rs1);
`USED_IREG (rd);
`USED_FREG (rs1);
end
7'h78: begin
// FMV.W.X=6
op_type = `OP_BITS'(`FPU_MISC);
op_mod = 6;
`USED_REG (rd_r, 1'b1, rd);
`USED_REG (rs1_r, 1'b0, rs1);
op_mod = 6;
`USED_FREG (rd);
`USED_IREG (rs1);
end
default:;
endcase
@@ -353,17 +348,17 @@ module VX_decode #(
3'h0: begin
op_type = `OP_BITS'(`GPU_TMC);
is_wstall = 1;
`USED_REG (rs1_r, 1'b0, rs1);
`USED_IREG (rs1);
end
3'h1: begin
op_type = `OP_BITS'(`GPU_WSPAWN);
`USED_REG (rs1_r, 1'b0, rs1);
`USED_REG (rs2_r, 1'b0, rs2);
`USED_IREG (rs1);
`USED_IREG (rs2);
end
3'h2: begin
op_type = `OP_BITS'(`GPU_SPLIT);
is_wstall = 1;
`USED_REG (rs1_r, 1'b0, rs1);
`USED_IREG (rs1);
end
3'h3: begin
op_type = `OP_BITS'(`GPU_JOIN);
@@ -372,8 +367,8 @@ module VX_decode #(
3'h4: begin
op_type = `OP_BITS'(`GPU_BAR);
is_wstall = 1;
`USED_REG (rs1_r, 1'b0, rs1);
`USED_REG (rs2_r, 1'b0, rs2);
`USED_IREG (rs1);
`USED_IREG (rs2);
end
default:;
endcase