From 90e21e8e58ac9f2d5a24bd98426110b68117cc11 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 17 Nov 2023 17:13:44 -0800 Subject: [PATCH] [CHANGE] Work around uninitialized signal issue with === operator It seems many of the initial arch/uarch states, including the GPR, are uninitialized in the VCS simulation, which results in functional errors caused by propagated X's. In this particular case it resulted in a dcache request not being fired due to the rs1 data for an lw instruction having values as X, causing the smem_unit to not arbitrate the request correctly. A workaround of this issue is to stop the X propagation by using the ===-operation instead of == in the GPR unit, which had been the main source of X propagation into the raddr port of the GPR. Also, we run the simulation with GSR_RESET set to 1 so that the contents of the GPR are initialized at the beginning of the simulation (however, this alone does not prevent reading in X's, hence this fix.) FIXME: This is a slight deviation from the upstream code; ideally, we want to do clean & full initialization of microarchitectural states. --- hw/rtl/libs/VX_dp_ram.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/rtl/libs/VX_dp_ram.sv b/hw/rtl/libs/VX_dp_ram.sv index 8ecfd837..4963c397 100644 --- a/hw/rtl/libs/VX_dp_ram.sv +++ b/hw/rtl/libs/VX_dp_ram.sv @@ -305,7 +305,7 @@ module VX_dp_ram #( `UNUSED_VAR (prev_waddr) assign rdata = ram[raddr]; end else begin - assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr]; + assign rdata = (prev_write && (prev_waddr === raddr)) ? prev_data : ram[raddr]; end end `endif