simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite
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@@ -96,12 +96,12 @@ public:
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return 0;
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}
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int upload(void* src, size_t dest_addr, size_t size, size_t src_offset) {
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int upload(const void* src, size_t dest_addr, size_t size, size_t src_offset) {
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auto asize = align_size(size, CACHE_BLOCK_SIZE);
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if (dest_addr + asize > ram_.size())
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return -1;
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ram_.write(dest_addr, asize, (uint8_t*)src + src_offset);
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ram_.write(dest_addr, (const uint8_t*)src + src_offset, asize);
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/*printf("VXDRV: upload %d bytes to 0x%x\n", size, dest_addr);
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for (int i = 0; i < size; i += 4) {
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@@ -111,12 +111,12 @@ public:
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return 0;
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}
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int download(const void* dest, size_t src_addr, size_t size, size_t dest_offset) {
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int download(void* dest, size_t src_addr, size_t size, size_t dest_offset) {
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size_t asize = align_size(size, CACHE_BLOCK_SIZE);
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if (src_addr + asize > ram_.size())
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return -1;
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ram_.read(src_addr, asize, (uint8_t*)dest + dest_offset);
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ram_.read(src_addr, (uint8_t*)dest + dest_offset, asize);
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/*printf("VXDRV: download %d bytes from 0x%x\n", size, src_addr);
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for (int i = 0; i < size; i += 4) {
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