wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

minor update

Browse Source
This commit is contained in:
Blaise Tine
2021-03-20 20:59:11 -04:00
parent 96a03a3edf
commit 8fa78ef059
5 changed files with 67 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
hw/rtl/tex_unit/VX_tex_addr_gen.v
View File

@@ -35,6 +35,8 @@ module VX_tex_addr_gen #(
output wire mem_req_valid, output wire mem_req_valid,
output wire [`NUM_THREADS-1:0] mem_req_tmask, output wire [`NUM_THREADS-1:0] mem_req_tmask,
output wire [`TEX_FILTER_BITS-1:0] mem_req_filter, output wire [`TEX_FILTER_BITS-1:0] mem_req_filter,
output wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_u,
output wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_v,
output wire [REQ_TAG_WIDTH-1:0] mem_req_tag, output wire [REQ_TAG_WIDTH-1:0] mem_req_tag,
output wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr, output wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr,
input wire mem_req_ready input wire mem_req_ready
@@ -114,14 +116,14 @@ module VX_tex_addr_gen #(
wire stall_out = mem_req_valid && ~mem_req_ready; wire stall_out = mem_req_valid && ~mem_req_ready;
VX_pipe_register #( VX_pipe_register #(
.DATAW (1 + `NUM_THREADS + `TEX_FILTER_BITS + REQ_TAG_WIDTH + (`NUM_THREADS * 4 * 32)), .DATAW (1 + `NUM_THREADS + `TEX_FILTER_BITS + REQ_TAG_WIDTH + (`NUM_THREADS * 4 * 32) + (`NUM_THREADS * `FIXED_FRAC)),
.RESETW (1) .RESETW (1)
) pipe_reg ( ) pipe_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.enable (~stall_out), .enable (~stall_out),
.data_in ({valid_in, req_tmask, filter, req_tag, addr}), .data_in ({valid_in, req_tmask, filter, req_tag, addr, u[0], v[0]}),
.data_out ({mem_req_valid, mem_req_tmask, mem_req_filter, mem_req_tag, mem_req_addr}) .data_out ({mem_req_valid, mem_req_tmask, mem_req_filter, mem_req_tag, mem_req_addr, mem_req_u, mem_req_v})
); );
assign ready_in = ~stall_out; assign ready_in = ~stall_out;

2
hw/rtl/tex_unit/VX_tex_define.vh
View File

@@ -26,6 +26,8 @@
`define MAX_COLOR_WIDTH 8 `define MAX_COLOR_WIDTH 8
`define NUM_COLOR_CHANNEL 4 `define NUM_COLOR_CHANNEL 4
`define TEX_COLOR_BITS 32
`define R5G6B5 `TEX_FORMAT_BITS'h1 `define R5G6B5 `TEX_FORMAT_BITS'h1
`define R8G8B8 `TEX_FORMAT_BITS'h2 `define R8G8B8 `TEX_FORMAT_BITS'h2
`define R8G8B8A8 `TEX_FORMAT_BITS'h3 `define R8G8B8A8 `TEX_FORMAT_BITS'h3

58
hw/rtl/tex_unit/VX_tex_format.v
View File

@@ -7,48 +7,42 @@ module VX_tex_format #(
input wire [`TEX_FORMAT_BITS-1:0] format, input wire [`TEX_FORMAT_BITS-1:0] format,
output wire [`NUM_COLOR_CHANNEL-1:0] color_enable, output wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
output wire [`MAX_COLOR_BITS-1:0] R, output wire [`TEX_COLOR_BITS-1:0] R,
output wire [`MAX_COLOR_BITS-1:0] G, output wire [`TEX_COLOR_BITS-1:0] G,
output wire [`MAX_COLOR_BITS-1:0] B, output wire [`TEX_COLOR_BITS-1:0] B,
output wire [`MAX_COLOR_BITS-1:0] A output wire [`TEX_COLOR_BITS-1:0] A
); );
`UNUSED_PARAM (CORE_ID) `UNUSED_PARAM (CORE_ID)
reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r; reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
reg [`MAX_COLOR_BITS-1:0] R_r; reg [`TEX_COLOR_BITS-1:0] R_r;
reg [`MAX_COLOR_BITS-1:0] G_r; reg [`TEX_COLOR_BITS-1:0] G_r;
reg [`MAX_COLOR_BITS-1:0] B_r; reg [`TEX_COLOR_BITS-1:0] B_r;
reg [`MAX_COLOR_BITS-1:0] A_r; reg [`TEX_COLOR_BITS-1:0] A_r;
always @(*) begin always @(*) begin
case (format) case (format)
`R5G6B5: `R5G6B5: begin
R_r = `MAX_COLOR_BITS'(texel_data[15:11]); R_r = `TEX_COLOR_BITS'(texel_data[15:11]);
G_r = `MAX_COLOR_BITS'(texel_data[10:5]); G_r = `TEX_COLOR_BITS'(texel_data[10:5]);
B_r = `MAX_COLOR_BITS'(texel_data[4:0]); B_r = `TEX_COLOR_BITS'(texel_data[4:0]);
A_r = {`MAX_COLOR_BITS{1'b0}}; A_r = {`TEX_COLOR_BITS{1'b0}};
color_enable_r = 4'b1110; color_enable_r = 4'b1110;
end
`R8G8B8: `R8G8B8: begin
R_r = `MAX_COLOR_BITS'(texel_data[23:16]); R_r = `TEX_COLOR_BITS'(texel_data[23:16]);
G_r = `MAX_COLOR_BITS'(texel_data[15:8]); G_r = `TEX_COLOR_BITS'(texel_data[15:8]);
B_r = `MAX_COLOR_BITS'(texel_data[7:0]); B_r = `TEX_COLOR_BITS'(texel_data[7:0]);
A_r = {`MAX_COLOR_BITS{1'b0}}; A_r = {`TEX_COLOR_BITS{1'b0}};
color_enable_r = 4'b1110; color_enable_r = 4'b1110;
end
`R8G8B8A8: default: begin // `R8G8B8A8:
R_r = `MAX_COLOR_BITS'(texel_data[31:24]); R_r = `TEX_COLOR_BITS'(texel_data[31:24]);
G_r = `MAX_COLOR_BITS'(texel_data[23:16]); G_r = `TEX_COLOR_BITS'(texel_data[23:16]);
B_r = `MAX_COLOR_BITS'(texel_data[15:8]); B_r = `TEX_COLOR_BITS'(texel_data[15:8]);
A_r = `MAX_COLOR_BITS'(texel_data[7:0]); A_r = `TEX_COLOR_BITS'(texel_data[7:0]);
color_enable_r = 4'b1111; color_enable_r = 4'b1111;
end
default:
R_r = `MAX_COLOR_BITS'(texel_data[23:16]);
G_r = `MAX_COLOR_BITS'(texel_data[15:8]);
B_r = `MAX_COLOR_BITS'(texel_data[7:0]);
A_r = {`MAX_COLOR_BITS{1'b0}};
color_enable_r = 4'b1110;
endcase endcase
end end

4
hw/rtl/tex_unit/VX_tex_sampler.v
View File

@@ -15,8 +15,8 @@ module VX_tex_sampler #(
input wire req_wb, input wire req_wb,
input wire [`TEX_FILTER_BITS-1:0] req_filter, input wire [`TEX_FILTER_BITS-1:0] req_filter,
input wire [`TEX_FORMAT_BITS-1:0] req_format, input wire [`TEX_FORMAT_BITS-1:0] req_format,
input wire [3:0][`FIXED_FRAC-1:0] req_ufrac, input wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] req_u,
input wire [3:0][`FIXED_FRAC-1:0] req_vfrac, input wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] req_v,
input wire [`NUM_THREADS-1:0][3:0][31:0] req_texels, input wire [`NUM_THREADS-1:0][3:0][31:0] req_texels,
output wire req_ready, output wire req_ready,

50
hw/rtl/tex_unit/VX_tex_unit.v
View File

@@ -18,7 +18,8 @@ module VX_tex_unit #(
VX_tex_rsp_if tex_rsp_if VX_tex_rsp_if tex_rsp_if
); );
localparam REQ_TAG_WIDTH = `TEX_FORMAT_BITS + `NW_BITS + 32 + `NR_BITS + 1; localparam REQ_TAG_WIDTH_A = `TEX_FORMAT_BITS + `NW_BITS + 32 + `NR_BITS + 1;
localparam REQ_TAG_WIDTH_M = (2 * `NUM_THREADS * `FIXED_FRAC) + REQ_TAG_WIDTH_A;
`UNUSED_PARAM (CORE_ID) `UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (reset) `UNUSED_VAR (reset)
@@ -70,19 +71,21 @@ module VX_tex_unit #(
wire mem_req_valid; wire mem_req_valid;
wire [`NUM_THREADS-1:0] mem_req_tmask; wire [`NUM_THREADS-1:0] mem_req_tmask;
wire [`TEX_FILTER_BITS-1:0] mem_req_filter; wire [`TEX_FILTER_BITS-1:0] mem_req_filter;
wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_u;
wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_v;
wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr; wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr;
wire [REQ_TAG_WIDTH-1:0] mem_req_tag; wire [REQ_TAG_WIDTH_A-1:0] mem_req_tag;
wire mem_req_ready; wire mem_req_ready;
wire mem_rsp_valid; wire mem_rsp_valid;
wire [`NUM_THREADS-1:0] mem_rsp_tmask; wire [`NUM_THREADS-1:0] mem_rsp_tmask;
wire [`TEX_FILTER_BITS-1:0] mem_rsp_filter; wire [`TEX_FILTER_BITS-1:0] mem_rsp_filter;
wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data; wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data;
wire [REQ_TAG_WIDTH-1:0] mem_rsp_tag; wire [REQ_TAG_WIDTH_M-1:0] mem_rsp_tag;
wire mem_rsp_ready; wire mem_rsp_ready;
VX_tex_addr_gen #( VX_tex_addr_gen #(
.REQ_TAG_WIDTH (REQ_TAG_WIDTH) .REQ_TAG_WIDTH (REQ_TAG_WIDTH_A)
) tex_addr_gen ( ) tex_addr_gen (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -108,6 +111,8 @@ module VX_tex_unit #(
.mem_req_valid (mem_req_valid), .mem_req_valid (mem_req_valid),
.mem_req_tmask (mem_req_tmask), .mem_req_tmask (mem_req_tmask),
.mem_req_filter (mem_req_filter), .mem_req_filter (mem_req_filter),
.mem_req_u (mem_req_u),
.mem_req_v (mem_req_v),
.mem_req_tag (mem_req_tag), .mem_req_tag (mem_req_tag),
.mem_req_addr (mem_req_addr), .mem_req_addr (mem_req_addr),
.mem_req_ready (mem_req_ready) .mem_req_ready (mem_req_ready)
@@ -117,7 +122,7 @@ module VX_tex_unit #(
VX_tex_memory #( VX_tex_memory #(
.CORE_ID (CORE_ID), .CORE_ID (CORE_ID),
.REQ_TAG_WIDTH (REQ_TAG_WIDTH) .REQ_TAG_WIDTH (REQ_TAG_WIDTH_M)
) tex_memory ( ) tex_memory (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -131,7 +136,7 @@ module VX_tex_unit #(
.req_tmask (mem_req_tmask), .req_tmask (mem_req_tmask),
.req_filter(mem_req_filter), .req_filter(mem_req_filter),
.req_addr (mem_req_addr), .req_addr (mem_req_addr),
.req_tag (mem_req_tag), .req_tag ({mem_req_u, mem_req_v, mem_req_tag}),
.req_ready (mem_req_ready), .req_ready (mem_req_ready),
// outputs // outputs
@@ -146,12 +151,14 @@ module VX_tex_unit #(
// apply sampler // apply sampler
wire [`TEX_FORMAT_BITS-1:0] rsp_format; wire [`TEX_FORMAT_BITS-1:0] rsp_format;
wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] rsp_u;
wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] rsp_v;
wire [`NW_BITS-1:0] rsp_wid; wire [`NW_BITS-1:0] rsp_wid;
wire [31:0] rsp_PC; wire [31:0] rsp_PC;
wire [`NR_BITS-1:0] rsp_rd; wire [`NR_BITS-1:0] rsp_rd;
wire rsp_wb; wire rsp_wb;
assign {rsp_format, rsp_wid, rsp_PC, rsp_rd, rsp_wb} = mem_rsp_tag; assign {rsp_format, rsp_u, rsp_v, rsp_wid, rsp_PC, rsp_rd, rsp_wb} = mem_rsp_tag;
VX_tex_sampler #( VX_tex_sampler #(
.CORE_ID (CORE_ID) .CORE_ID (CORE_ID)
@@ -165,6 +172,8 @@ module VX_tex_unit #(
.req_texels (mem_rsp_data), .req_texels (mem_rsp_data),
.req_filter (mem_rsp_filter), .req_filter (mem_rsp_filter),
.req_format (rsp_format), .req_format (rsp_format),
.req_u (rsp_u),
.req_v (rsp_v),
.req_wid (rsp_wid), .req_wid (rsp_wid),
.req_PC (rsp_PC), .req_PC (rsp_PC),
.req_rd (rsp_rd), .req_rd (rsp_rd),
@@ -183,19 +192,20 @@ module VX_tex_unit #(
); );
`ifdef DBG_PRINT_TEX `ifdef DBG_PRINT_TEX
always @(posedge clk) begin for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
if (tex_csr_if.write_enable always @(posedge clk) begin
&& (tex_csr_if.write_addr >= `CSR_TEX_BEGIN(0) if (tex_csr_if.write_enable
&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(`CSR_TEX_STATES))) begin && (tex_csr_if.write_addr >= `CSR_TEX_BEGIN(i)
$display("%t: core%0d-tex_csr: csr_tex0_addr, csr_data=%0h", $time, CORE_ID, tex_addr[0]); && tex_csr_if.write_addr < `CSR_TEX_BEGIN(i+1))) begin
$display("%t: core%0d-tex_csr: csr_tex0_format, csr_data=%0h", $time, CORE_ID, tex_format[0]); $display("%t: core%0d-tex_csr: csr_tex%d_addr, csr_data=%0h", $time, CORE_ID, i, tex_addr[i]);
$display("%t: core%0d-tex_csr: csr_tex0_width, csr_data=%0h", $time, CORE_ID, tex_width[0]); $display("%t: core%0d-tex_csr: csr_tex%d_format, csr_data=%0h", $time, CORE_ID, i, tex_format[i]);
$display("%t: core%0d-tex_csr: csr_tex0_height, csr_data=%0h", $time, CORE_ID, tex_height[0]); $display("%t: core%0d-tex_csr: csr_tex%d_width, csr_data=%0h", $time, CORE_ID, i, tex_width[i]);
$display("%t: core%0d-tex_csr: CSR_TEX0_PITCH, csr_data=%0h", $time, CORE_ID, tex_stride[0]); $display("%t: core%0d-tex_csr: csr_tex%d_height, csr_data=%0h", $time, CORE_ID, i, tex_height[i]);
$display("%t: core%0d-tex_csr: csr_tex0_wrap_u, csr_data=%0h", $time, CORE_ID, tex_wrap_u[0]); $display("%t: core%0d-tex_csr: csr_tex%d_stride, csr_data=%0h", $time, CORE_ID, i, tex_stride[i]);
$display("%t: core%0d-tex_csr: csr_tex0_wrap_v, csr_data=%0h", $time, CORE_ID, tex_wrap_v[0]); $display("%t: core%0d-tex_csr: csr_tex%d_wrap_u, csr_data=%0h", $time, CORE_ID, i, tex_wrap_u[i]);
$display("%t: core%0d-tex_csr: csr_tex0_min_filter, csr_data=%0h", $time, CORE_ID, tex_min_filter[0]); $display("%t: core%0d-tex_csr: csr_tex%d_wrap_v, csr_data=%0h", $time, CORE_ID, i, tex_wrap_v[i]);
$display("%t: core%0d-tex_csr: csr_tex0_max_filter, csr_data=%0h", $time, CORE_ID, tex_max_filter[0]); $display("%t: core%0d-tex_csr: csr_tex%d_filter, csr_data=%0h", $time, CORE_ID, i, tex_filter[i]);
end
end end
end end
`endif `endif