minor update

hw/rtl/VX_lsu_unit.sv

@@ -303,7 +303,7 @@ module VX_lsu_unit #(
     `SCOPE_ASSIGN (dcache_rsp_data,  dcache_rsp_if.data);
     `SCOPE_ASSIGN (dcache_rsp_tag,   mbuf_raddr);
 
-`ifndef __SYNTHESIS__
+`ifndef SYNTHESIS
     reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs;
     wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
 

hw/rtl/VX_platform.vh

@@ -1,7 +1,7 @@
 `ifndef VX_PLATFORM
 `define VX_PLATFORM
 
-`ifndef __SYNTHESIS__
+`ifndef SYNTHESIS
 `include "util_dpi.vh"
 `endif
 
@@ -9,7 +9,7 @@
 
 ///////////////////////////////////////////////////////////////////////////////
 
-`ifndef __SYNTHESIS__
+`ifndef SYNTHESIS
 
 `ifndef NDEBUG
     `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \
@@ -70,7 +70,7 @@
 `define TRACING_ON  /* verilator tracing_on */
 `define TRACING_OFF /* verilator tracing_off */
 
-`else // __SYNTHESIS__
+`else // SYNTHESIS
 
 `define DEBUG_BLOCK(x)
 `define IGNORE_UNUSED_BEGIN
@@ -87,7 +87,7 @@
 `define TRACING_ON
 `define TRACING_OFF
 
-`endif // __SYNTHESIS__
+`endif // SYNTHESIS
 
 ///////////////////////////////////////////////////////////////////////////////
 

hw/rtl/libs/VX_dp_ram.sv

@@ -34,7 +34,7 @@ module VX_dp_ram #(
         end                                       \
     end
 
-`ifdef __SYNTHESIS__
+`ifdef SYNTHESIS
     if (LUTRAM) begin
         if (OUT_REG) begin        
             reg [DATAW-1:0] rdata_r;

hw/rtl/libs/VX_sp_ram.sv

@@ -33,7 +33,7 @@ module VX_sp_ram #(
         end                                       \
     end
 
-`ifdef __SYNTHESIS__
+`ifdef SYNTHESIS
     if (LUTRAM) begin
         if (OUT_REG) begin        
             reg [DATAW-1:0] rdata_r;