RTL code refactoring

2020-04-20 14:05:08 -04:00
parent 1a2823da0d
commit 8e7046a388
15 changed files with 53 additions and 484 deletions
--- a/hw/unit_tests/generic_queue/testbench.v
+++ b/hw/unit_tests/generic_queue/testbench.v
@@ -17,10 +17,10 @@ module testbench();
  VX_generic_queue #(.DATAW(4), .SIZE(4)) dut (
                                .clk(clk), 
                                .reset(reset), 
-                                .data_i(in_data), 
+                                .data_in(in_data), 
                                .push(push), 
                                .pop(pop), 
-                                .data_o(out_data), 
+                                .data_out(out_data), 
                                .empty(empty), 
                                .full(full));