RTL code refactoring

2020-04-20 14:05:08 -04:00
parent 1a2823da0d
commit 8e7046a388
15 changed files with 53 additions and 484 deletions
--- a/hw/rtl/pipe_regs/VX_i_d_reg.v
+++ b/hw/rtl/pipe_regs/VX_i_d_reg.v
@@ -14,7 +14,9 @@ module VX_i_d_reg (
 	wire stall = freeze_i == 1'b1;


-	VX_generic_register #( .N( 64 + `NW_BITS-1 + 1 + `NUM_THREADS ) ) i_d_reg (
+	VX_generic_register #(
+		.N(64 + `NW_BITS-1 + 1 + `NUM_THREADS)
+	) i_d_reg (
 		.clk  (clk),
 		.reset(reset),
 		.stall(stall),