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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 14:05:08 -04:00
parent 1a2823da0d
commit 8e7046a388
15 changed files with 53 additions and 484 deletions
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14
hw/rtl/pipe_regs/VX_f_d_reg.v
View File

@@ -1,19 +1,21 @@
`include "../VX_define.vh"
module VX_f_d_reg (
input wire clk,
input wire reset,
input wire freeze_i,
input wire clk,
input wire reset,
input wire freeze_i,
VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_if fd_inst_meta_de
VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_if fd_inst_meta_de
);
wire flush = 1'b0;
wire stall = freeze_i == 1'b1;
VX_generic_register #( .N(64+`NW_BITS-1+1+`NUM_THREADS) ) f_d_reg (
VX_generic_register #(
.N(64+`NW_BITS-1+1+`NUM_THREADS)
) f_d_reg (
.clk (clk),
.reset(reset),
.stall(stall),

4
hw/rtl/pipe_regs/VX_i_d_reg.v
View File

@@ -14,7 +14,9 @@ module VX_i_d_reg (
wire stall = freeze_i == 1'b1;
VX_generic_register #( .N( 64 + `NW_BITS-1 + 1 + `NUM_THREADS ) ) i_d_reg (
VX_generic_register #(
.N(64 + `NW_BITS-1 + 1 + `NUM_THREADS)
) i_d_reg (
.clk (clk),
.reset(reset),
.stall(stall),