RTL code refactoring

2020-04-20 14:05:08 -04:00
parent 1a2823da0d
commit 8e7046a388
15 changed files with 53 additions and 484 deletions
--- a/hw/rtl/cache/VX_prefetcher.v
+++ b/hw/rtl/cache/VX_prefetcher.v
@@ -40,10 +40,10 @@ module VX_prefetcher #(
 		.reset   (reset),

 		.push    (dram_req && !current_full && !pref_pop),
-		.data_i (dram_req_addr & `BASE_ADDR_MASK),
+		.data_in (dram_req_addr & `BASE_ADDR_MASK),

 		.pop     (update_use),
-		.data_o(current_addr),
+		.data_out(current_addr),

 		.empty   (current_empty),
 		.full    (current_full)