RTL code refactoring

2020-04-20 14:05:08 -04:00
parent 1a2823da0d
commit 8e7046a388
15 changed files with 53 additions and 484 deletions
--- a/hw/rtl/cache/VX_cache_dfq_queue.v
+++ b/hw/rtl/cache/VX_cache_dfq_queue.v
@@ -79,9 +79,9 @@ module VX_cache_dfq_queue #(
 		.clk     (clk),
 		.reset   (reset),
 		.push    (push_qual),
-		.data_i ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}),
+		.data_in ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}),
 		.pop     (pop_qual),
-		.data_o({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}),
+		.data_out({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}),
 		.empty   (o_empty),
 		.full    (dfqq_full)
 	);