round robin warp scheduling

hw/rtl/VX_config.vh

@@ -274,7 +274,7 @@
 
 // Size of LSU Request Queue
 `ifndef LSUQ_SIZE
-`define LSUQ_SIZE   (8 * (`NUM_THREADS / `NUM_LSU_LANES))
+`define LSUQ_SIZE   (2 * `NUM_WARPS * (`NUM_THREADS / `NUM_LSU_LANES))
 `endif
 
 // LSU Duplicate Address Check

hw/rtl/core/VX_schedule.sv

@@ -308,10 +308,11 @@ module VX_schedule import VX_gpu_pkg::*; #(
 
     wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls);
 
-    VX_lzc #(
-        .N       (`NUM_WARPS),
-        .REVERSE (1)
+    VX_lzc_rr #(
+        .N       (`NUM_WARPS)
     ) wid_select (
+        .clk       (clk),
+        .reset     (reset),
         .data_in   (ready_warps),
         .data_out  (schedule_wid),
         .valid_out (schedule_valid)

hw/rtl/libs/VX_lzc.sv

@@ -21,7 +21,7 @@ module VX_lzc #(
 ) (
     input  wire [N-1:0]    data_in,
     output wire [LOGN-1:0] data_out,
-    output wire            valid_out
+    output logic           valid_out
 );
     if (N == 1) begin
 
@@ -33,11 +33,11 @@ module VX_lzc #(
     end else begin
 
         wire [N-1:0][LOGN-1:0] indices;
-
+    
         for (genvar i = 0; i < N; ++i) begin
             assign indices[i] = REVERSE ? LOGN'(i) : LOGN'(N-1-i);
         end
-
+    
         VX_find_first #(
             .N       (N),
             .DATAW   (LOGN),
@@ -51,5 +51,42 @@ module VX_lzc #(
 
     end
   
+endmodule
+
+module VX_lzc_rr #(
+    parameter N       = 2
+) (
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire [N-1:0]          data_in,
+    output logic [$clog2(N)-1:0] data_out,
+    output logic                 valid_out
+);
+
+    logic [$clog2(N)-1:0] current_idx;
+
+    always @(*) begin
+        integer i;
+        data_out = 0;
+        for (i = 0; i < N; i += 1) begin
+            if (data_in[(current_idx + i) % N] == 1'b1) begin
+                data_out = (current_idx + i) % N;
+                break;
+            end
+        end
+    end
+
+    assign valid_out = |data_in;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            current_idx <= 0;
+        end else begin
+            if (valid_out) begin
+                current_idx = (current_idx + 1) % N;
+            end
+        end
+    end
+
 endmodule
 `TRACING_ON