Quartus + GPR evaluation

rtl/quartus/Makefile

@@ -0,0 +1,70 @@
+PROJECT = VX_gpr_syn
+TOP_LEVEL_ENTITY = VX_gpr_syn
+SRC_FILE = VX_gpr_syn.v
+PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+
+# Part, Family
+FAMILY = "Arria 10"
+DEVICE = 10AX115N4F45I3SG   
+
+# Executable Configuration
+SYN_ARGS = --read_settings_files=on
+FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
+ASM_ARGS =
+STA_ARGS = --do_report_timing
+
+# Build targets
+all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt
+
+syn: smart.log $(PROJECT).syn.rpt
+
+fit: smart.log $(PROJECT).fit.rpt
+
+asm: smart.log $(PROJECT).asm.rpt
+
+sta: smart.log $(PROJECT).sta.rpt
+
+smart: smart.log
+
+# Target implementations
+STAMP = echo done >
+
+$(PROJECT).syn.rpt: syn.chg $(SOURCE_FILES) 
+	/tools/reconfig/intel/18.0/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: fit.chg $(PROJECT).syn.rpt
+	/tools/reconfig/intel/18.0/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt
+	/tools/reconfig/intel/18.0/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS)
+
+$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt
+	/tools/reconfig/intel/18.0/quartus/bin/quartus_sta $(PROJECT)  $(STA_ARGS) 
+
+smart.log: $(PROJECT_FILES)
+	/tools/reconfig/intel/18.0/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+# Project initialization
+$(PROJECT_FILES):
+	/tools/reconfig/intel/18.0/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc
+	
+syn.chg:
+	$(STAMP) syn.chg
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
+
+program: $(PROJECT).sof
+	quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
+	
+clean:
+	rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox

rtl/quartus/project.tcl

@@ -0,0 +1,86 @@
+package require cmdline
+
+set options { \
+    { "project.arg" "" "Project name" } \
+    { "family.arg" "" "Device family name" } \
+    { "device.arg" "" "Device name" } \
+    { "top.arg" "" "Top level module" } \
+    { "sdc.arg" "" "Timing Design Constraints file" } \
+    { "src.arg" "" "Verilog source file" } \
+}
+
+array set opts [::cmdline::getoptions quartus(args) $options]
+
+project_new $opts(project) -overwrite
+
+set_global_assignment -name FAMILY $opts(family)
+set_global_assignment -name DEVICE $opts(device)
+set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
+
+set_global_assignment -name SEARCH_PATH  ../
+
+set_global_assignment -name VERILOG_FILE ../VX_define.v
+
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
+set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
+
+set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
+set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
+set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
+set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
+
+set_global_assignment -name VERILOG_FILE ../VX_alu.v
+set_global_assignment -name VERILOG_FILE ../VX_back_end.v
+set_global_assignment -name VERILOG_FILE ../VX_context.v
+set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
+set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v
+set_global_assignment -name VERILOG_FILE ../VX_decode.v
+set_global_assignment -name VERILOG_FILE ../VX_define.v
+set_global_assignment -name VERILOG_FILE ../VX_execute.v
+set_global_assignment -name VERILOG_FILE ../VX_fetch.v
+set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
+set_global_assignment -name VERILOG_FILE ../VX_front_end.v
+set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
+set_global_assignment -name VERILOG_FILE ../VX_gpr.v
+set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
+set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
+set_global_assignment -name VERILOG_FILE ../VX_memory.v
+set_global_assignment -name VERILOG_FILE ../VX_register_file.v
+set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
+set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
+set_global_assignment -name VERILOG_FILE ../VX_warp.v
+set_global_assignment -name VERILOG_FILE ../VX_writeback.v
+set_global_assignment -name VERILOG_FILE ../Vortex.v
+
+set_global_assignment -name SDC_FILE vortex.sdc
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+
+project_close
+
+# set_global_assignment -name VERILOG_FILE $opts(src)
+

rtl/quartus/vortex.ini

@@ -0,0 +1,40 @@
+load_package flow
+
+
+set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
+set_global_assignment -name VERILOG_FILE ../VX_gpr.v
+set_global_assignment -name SDC_FILE vortex.sdc
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+
+# pins configuration
+package require cmdline
+
+proc make_all_pins_virtual { args } {
+
+    set options {\
+        { "exclude.arg" "" "List of signals to exclude" } \
+    }
+    array set opts [::cmdline::getoptions quartus(args) $options]
+
+    remove_all_instance_assignments -name VIRTUAL_PIN
+    execute_module -tool map
+    set name_ids [get_names -filter * -node_type pin]
+
+    foreach_in_collection name_id $name_ids {
+        set pin_name [get_name_info -info full_path $name_id]
+
+        if { -1 == [lsearch -exact $opts(excludes) $pin_name] } {
+            post_message "Making VIRTUAL_PIN assignment to $pin_name"
+            set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+        } else {
+            post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
+        }
+    }
+    export_assignments
+}
+
+
+make_all_pins_virtual -exclude { clk, reset }

rtl/quartus/vortex.sdc

@@ -0,0 +1 @@
+create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]