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Quartus + GPR evaluation

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This commit is contained in:
felsabbagh3
2019-09-10 20:23:01 -04:00
parent 4e8da1811a
commit 8d143d7739
68 changed files with 5345 additions and 3066 deletions
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0
rtl/interfaces/._VX_forward_csr_response_inter.sv → rtl/interfaces/._VX_forward_csr_response_inter.v
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0
rtl/interfaces/._VX_forward_mem_inter.sv → rtl/interfaces/._VX_forward_mem_inter.v
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0
rtl/interfaces/._VX_gpr_read_inter.sv → rtl/interfaces/._VX_gpr_read_inter.v
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15
rtl/interfaces/VX_branch_response_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_BRANCH_RSP
@@ -11,19 +11,6 @@ interface VX_branch_response_inter ();
wire[31:0] branch_dest;
wire[`NW_M1:0] branch_warp_num;
// source-side view
modport snk (
input branch_dir,
input branch_dest
);
// source-side view
modport src (
output branch_dir,
output branch_dest
);
endinterface

17
rtl/interfaces/VX_csr_write_request_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_CSR_W_REQ
@@ -11,21 +11,6 @@ interface VX_csr_write_request_inter ();
wire[11:0] csr_address;
wire[31:0] csr_result;
// source-side view
modport snk (
input is_csr,
input csr_address,
input csr_result
);
// source-side view
modport src (
output is_csr,
output csr_address,
output csr_result
);
endinterface

22
rtl/interfaces/VX_dcache_request_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_DCACHE_REQ
@@ -13,26 +13,6 @@ interface VX_dcache_request_inter ();
wire out_cache_driver_in_valid[`NT_M1:0];
wire[31:0] out_cache_driver_in_data[`NT_M1:0];
// source-side view
modport snk (
input out_cache_driver_in_address,
input out_cache_driver_in_mem_read,
input out_cache_driver_in_mem_write,
input out_cache_driver_in_valid,
input out_cache_driver_in_data
);
// source-side view
modport src (
output out_cache_driver_in_address,
output out_cache_driver_in_mem_read,
output out_cache_driver_in_mem_write,
output out_cache_driver_in_valid,
output out_cache_driver_in_data
);
endinterface

14
rtl/interfaces/VX_dcache_response_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_DCACHE_RSP
@@ -9,18 +9,6 @@ interface VX_dcache_response_inter ();
wire[31:0] in_cache_driver_out_data[`NT_M1:0];
// source-side view
modport snk (
input in_cache_driver_out_data
);
// source-side view
modport src (
output in_cache_driver_out_data
);
endinterface

32
rtl/interfaces/VX_forward_csr_response_inter.sv
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@@ -1,32 +0,0 @@
`include "VX_define.v"
`ifndef VX_FWD_CSR_RSP
`define VX_FWD_CSR_RSP
interface VX_forward_csr_response_inter ();
/* verilator lint_off UNUSED */
wire csr_fwd;
wire[31:0] csr_fwd_data;
/* verilator lint_on UNUSED */
// source-side view
modport snk (
input csr_fwd,
input csr_fwd_data
);
// source-side view
modport src (
output csr_fwd,
output csr_fwd_data
);
endinterface
`endif

17
rtl/interfaces/VX_forward_csr_response_inter.v Normal file
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@@ -0,0 +1,17 @@
`include "../VX_define.v"
`ifndef VX_FWD_CSR_RSP
`define VX_FWD_CSR_RSP
interface VX_forward_csr_response_inter ();
/* verilator lint_off UNUSED */
wire csr_fwd;
wire[31:0] csr_fwd_data;
/* verilator lint_on UNUSED */
endinterface
`endif

22
rtl/interfaces/VX_forward_exe_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FWD_EXE
@@ -13,26 +13,6 @@ interface VX_forward_exe_inter ();
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input dest,
input wb,
input alu_result,
input PC_next,
input warp_num
);
// source-side view
modport src (
output dest,
output wb,
output alu_result,
output PC_next,
output warp_num
);
endinterface

42
rtl/interfaces/VX_forward_mem_inter.sv
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@@ -1,42 +0,0 @@
`include "VX_define.v"
`ifndef VX_FWD_MEM
`define VX_FWD_MEM
interface VX_forward_mem_inter ();
wire[4:0] dest;
wire[1:0] wb;
wire[`NT_M1:0][31:0] alu_result;
wire[`NT_M1:0][31:0] mem_data;
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input dest,
input wb,
input alu_result,
input mem_data,
input PC_next,
input warp_num
);
// source-side view
modport src (
output dest,
output wb,
output alu_result,
output mem_data,
output PC_next,
output warp_num
);
endinterface
`endif

20
rtl/interfaces/VX_forward_mem_inter.v Normal file
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@@ -0,0 +1,20 @@
`include "../VX_define.v"
`ifndef VX_FWD_MEM
`define VX_FWD_MEM
interface VX_forward_mem_inter ();
wire[4:0] dest;
wire[1:0] wb;
wire[`NT_M1:0][31:0] alu_result;
wire[`NT_M1:0][31:0] mem_data;
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
endinterface
`endif

17
rtl/interfaces/VX_forward_reqeust_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FWD_REQ
@@ -11,21 +11,6 @@ interface VX_forward_reqeust_inter ();
wire[4:0] src2;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input src1,
input src2,
input warp_num
);
// source-side view
modport src (
output src1,
output src2,
output warp_num
);
endinterface

20
rtl/interfaces/VX_forward_response_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FWD_RSP
@@ -12,24 +12,6 @@ interface VX_forward_response_inter ();
wire[`NT_M1:0][31:0] src1_fwd_data;
wire[`NT_M1:0][31:0] src2_fwd_data;
// source-side view
modport snk (
input src1_fwd,
input src2_fwd,
input src1_fwd_data,
input src2_fwd_data
);
// source-side view
modport src (
output src1_fwd,
output src2_fwd,
output src1_fwd_data,
output src2_fwd_data
);
endinterface

23
rtl/interfaces/VX_forward_wb_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FWD_WB
@@ -14,27 +14,6 @@ interface VX_forward_wb_inter ();
wire[31:0] PC_next;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input dest,
input wb,
input alu_result,
input mem_data,
input PC_next,
input warp_num
);
// source-side view
modport src (
output dest,
output wb,
output alu_result,
output mem_data,
output PC_next,
output warp_num
);
endinterface

55
rtl/interfaces/VX_frE_to_bckE_req_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_FrE_to_BE_INTER
@@ -30,59 +30,6 @@ interface VX_frE_to_bckE_req_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input csr_address,
input is_csr,
input csr_mask,
input rd,
input rs1,
input rs2,
input a_reg_data,
input b_reg_data,
input alu_op,
input wb,
input rs2_src,
input itype_immed,
input mem_read,
input mem_write,
input branch_type,
input upper_immed,
input curr_PC,
input jal,
input jal_offset,
input PC_next,
input valid,
input warp_num
);
// source-side view
modport src (
output csr_address,
output is_csr,
output csr_mask,
output rd,
output rs1,
output rs2,
output a_reg_data,
output b_reg_data,
output alu_op,
output wb,
output rs2_src,
output itype_immed,
output mem_read,
output mem_write,
output branch_type,
output upper_immed,
output curr_PC,
output jal,
output jal_offset,
output PC_next,
output valid,
output warp_num
);
endinterface

23
rtl/interfaces/VX_gpr_clone_inter.v
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@@ -1,27 +1,16 @@
`include "../VX_define.v"
`ifndef VX_GPR_CLONE_INTER
`define VX_GPR_CLONE_INTER
interface VX_gpr_clone_inter ();
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
modport snk (
input is_clone,
input warp_num
);
modport src (
output is_clone,
output warp_num
);
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface

14
rtl/interfaces/VX_gpr_jal_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`ifndef VX_GPR_JAL_INTER
`define VX_GPR_JAL_INTER
@@ -7,18 +7,6 @@
interface VX_gpr_jal_inter ();
wire is_jal;
wire[31:0] curr_PC;
modport snk (
input is_jal,
input curr_PC
);
modport src (
output is_jal,
output curr_PC
);
endinterface

2
rtl/interfaces/VX_gpr_read_inter.sv → rtl/interfaces/VX_gpr_read_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`ifndef VX_GPR_READ
`define VX_GPR_READ

14
rtl/interfaces/VX_gpr_wspawn_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`ifndef VX_GPR_WSPAWN_INTER
`define VX_GPR_WSPAWN_INTER
@@ -11,18 +11,6 @@ interface VX_gpr_wspawn_inter ();
// wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
modport snk (
input is_wspawn,
input which_wspawn
);
modport src (
output is_wspawn,
output which_wspawn
);
endinterface

14
rtl/interfaces/VX_icache_request_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_ICACHE_REQ
@@ -9,18 +9,6 @@ interface VX_icache_request_inter ();
wire[31:0] pc_address;
// source-side view
modport snk (
input pc_address
);
// source-side view
modport src (
output pc_address
);
endinterface

13
rtl/interfaces/VX_icache_response_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_ICACHE_RSP
@@ -11,17 +11,6 @@ interface VX_icache_response_inter ();
// wire stall;
wire[31:0] instruction;
// source-side view
modport snk (
input instruction
);
// source-side view
modport src (
output instruction
);
endinterface

25
rtl/interfaces/VX_inst_mem_wb_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_MEM_WB_INST_INTER
@@ -15,29 +15,6 @@ interface VX_inst_mem_wb_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
// source-side view
modport snk (
input alu_result,
input mem_result,
input rd,
input wb,
input PC_next,
input valid,
input warp_num
);
// source-side view
modport src (
output alu_result,
output mem_result,
output rd,
output wb,
output PC_next,
output valid,
output warp_num
);
endinterface

18
rtl/interfaces/VX_inst_meta_inter.v
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@@ -1,4 +1,4 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_F_D_INTER
@@ -10,22 +10,6 @@ interface VX_inst_meta_inter ();
wire[`NW_M1:0] warp_num;
wire[`NT_M1:0] valid;
// source-side view
modport snk (
input instruction,
input inst_pc,
input warp_num,
input valid
);
// sink-side view
modport src (
output instruction,
output inst_pc,
output warp_num,
output valid
);
endinterface

20
rtl/interfaces/VX_jal_response_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_JAL_RSP
@@ -10,23 +10,7 @@ interface VX_jal_response_inter ();
wire jal;
wire[31:0] jal_dest;
wire[`NW_M1:0] jal_warp_num;
// source-side view
modport snk (
input jal,
input jal_dest,
input jal_warp_num
);
// source-side view
modport src (
output jal,
output jal_dest,
output jal_warp_num
);
endinterface

43
rtl/interfaces/VX_mem_req_inter.v
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@@ -1,3 +1,9 @@
`include "../VX_define.v"
`ifndef VX_MEM_REQ_IN
`define VX_MEM_REQ_IN
interface VX_mem_req_inter ();
wire[`NT_M1:0][31:0] alu_result;
@@ -16,40 +22,7 @@ interface VX_mem_req_inter ();
wire[`NW_M1:0] warp_num;
modport snk (
input alu_result,
input mem_read,
input mem_write,
input rd,
input wb,
input rs1,
input rs2,
input rd2,
input PC_next,
input curr_PC,
input branch_offset,
input branch_type,
input valid,
input warp_num
);
endinterface
modport src (
output alu_result,
output mem_read,
output mem_write,
output rd,
output wb,
output rs1,
output rs2,
output rd2,
output PC_next,
output curr_PC,
output branch_offset,
output branch_type,
output valid,
output warp_num
);
endinterface
`endif

25
rtl/interfaces/VX_mw_wb_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_MW_WB_INTER
@@ -15,29 +15,6 @@ interface VX_mw_wb_inter ();
wire[`NT_M1:0] valid;
wire [`NW_M1:0] warp_num;
// source-side view
modport snk (
input alu_result,
input mem_result,
input rd,
input wb,
input PC_next,
input valid,
input warp_num
);
// source-side view
modport src (
input alu_result,
input mem_result,
input rd,
input wb,
input PC_next,
input valid,
input warp_num
);
endinterface

23
rtl/interfaces/VX_warp_ctl_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
`ifndef VX_WARP_CTL_INTER
@@ -14,27 +14,6 @@ interface VX_warp_ctl_inter ();
wire[31:0] wspawn_pc;
wire ebreak;
// source-side view
modport snk (
input warp_num,
input change_mask,
input thread_mask,
input wspawn,
input wspawn_pc,
input ebreak
);
// source-side view
modport src (
output warp_num,
output change_mask,
output thread_mask,
output wspawn,
output wspawn_pc,
output ebreak
);
endinterface

20
rtl/interfaces/VX_wb_inter.v
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@@ -1,3 +1,4 @@
`include "../VX_define.v"
`ifndef VX_WB_INTER
@@ -12,25 +13,6 @@ interface VX_wb_inter ();
wire[`NT_M1:0] wb_valid;
wire[`NW_M1:0] wb_warp_num;
modport snk (
input write_data,
input rd,
input wb,
input wb_valid,
input wb_warp_num
);
modport src (
output write_data,
output rd,
output wb,
output wb_valid,
output wb_warp_num
);
endinterface