wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Quartus + GPR evaluation

Browse Source
This commit is contained in:
felsabbagh3
2019-09-10 20:23:01 -04:00
parent 4e8da1811a
commit 8d143d7739
68 changed files with 5345 additions and 3066 deletions
Download Patch File Download Diff File Expand all files Collapse all files

72
rtl/VX_gpr.v
View File

@@ -4,7 +4,6 @@
module VX_gpr (
input wire clk,
input wire valid_write_request,
input wire valid_read_request,
VX_gpr_read_inter VX_gpr_read,
VX_wb_inter VX_writeback_inter,
@@ -20,23 +19,60 @@ module VX_gpr (
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
// assign read_enable = valid_request;
genvar thread_index;
always_ff@(posedge clk)
begin
if (write_enable) begin
for (thread_index = 0; thread_index <= `NT_M1; thread_index = thread_index + 1) begin
if (VX_writeback_inter.wb_valid[thread_index]) begin
gpr[VX_writeback_inter.rd][thread_index] <= VX_writeback_inter.write_data[thread_index];
end
end
end
end
// // Using Registers
// integer thread_index;
// always_ff@(posedge clk)
// begin
// if (write_enable) begin
// for (thread_index = 0; thread_index <= `NT_M1; thread_index = thread_index + 1) begin
// if (VX_writeback_inter.wb_valid[thread_index]) begin
// gpr[VX_writeback_inter.rd][thread_index] <= VX_writeback_inter.write_data[thread_index];
// end
// end
// end
// out_a_reg_data <= gpr[VX_gpr_read.rs1];
// out_b_reg_data <= gpr[VX_gpr_read.rs2];
// end
// USING RAM blocks
// First RAM
integer thread_index_1;
always_ff@(posedge clk)
begin
if (write_enable) begin
for (thread_index_1 = 0; thread_index_1 <= `NT_M1; thread_index_1 = thread_index_1 + 1) begin
if (VX_writeback_inter.wb_valid[thread_index_1]) begin
gpr[VX_writeback_inter.rd][thread_index_1] <= VX_writeback_inter.write_data[thread_index_1];
end
end
end
end
always @(negedge clk) begin
out_a_reg_data <= gpr[VX_gpr_read.rs1];
end
// Second RAM
integer thread_index_2;
always_ff@(posedge clk)
begin
if (write_enable) begin
for (thread_index_2 = 0; thread_index_2 <= `NT_M1; thread_index_2 = thread_index_2 + 1) begin
if (VX_writeback_inter.wb_valid[thread_index_2]) begin
gpr[VX_writeback_inter.rd][thread_index_2] <= VX_writeback_inter.write_data[thread_index_2];
end
end
end
end
always @(negedge clk) begin
out_b_reg_data <= gpr[VX_gpr_read.rs2];
end
always @(negedge clk) begin
if (valid_read_request) begin
out_a_reg_data <= gpr[VX_gpr_read.rs1];
out_b_reg_data <= gpr[VX_gpr_read.rs2];
end
end
endmodule