From dce5e79f65374866d4f08572ea44bae18bd085d7 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 15 May 2023 18:53:24 -0400 Subject: [PATCH 1/5] toolchain update --- ci/prebuilt.sh | 12 ++++++------ ci/toolchain_install.sh | 14 +++++++------- sim/rtlsim/Makefile | 2 +- sim/rtlsim/processor.cpp | 4 ++-- sim/vlsim/Makefile | 2 +- sim/vlsim/opae_sim.cpp | 2 +- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/ci/prebuilt.sh b/ci/prebuilt.sh index cc9ff3dd..6b0f81e7 100755 --- a/ci/prebuilt.sh +++ b/ci/prebuilt.sh @@ -23,17 +23,17 @@ riscv() llvm() { echo "prebuilt llvm-riscv..." - tar -C $SRCDIR -cvjf llvm-riscv.tar.bz2 llvm-riscv - split -b 50M llvm-riscv.tar.bz2 "llvm-riscv.tar.bz2.part" - mv llvm-riscv.tar.bz2.part* $DESTDIR/llvm-riscv/$OS_DIR - rm llvm-riscv.tar.bz2 + tar -C $SRCDIR -cvjf llvm-vortex1.tar.bz2 llvm-riscv + split -b 50M llvm-vortex1.tar.bz2 "llvm-vortex1.tar.bz2.part" + mv llvm-vortex1.tar.bz2.part* $DESTDIR/llvm-vortex/$OS_DIR + rm llvm-vortex1.tar.bz2 } pocl() { echo "prebuilt pocl..." - tar -C $SRCDIR -cvjf pocl.tar.bz2 pocl - mv pocl.tar.bz2 $DESTDIR/pocl/$OS_DIR + tar -C $SRCDIR -cvjf pocl1.tar.bz2 pocl + mv pocl1.tar.bz2 $DESTDIR/pocl/$OS_DIR } verilator() diff --git a/ci/toolchain_install.sh b/ci/toolchain_install.sh index 5194974b..6422300d 100755 --- a/ci/toolchain_install.sh +++ b/ci/toolchain_install.sh @@ -37,20 +37,20 @@ llvm() { for x in {a..b} do - wget $REPOSITORY/llvm-riscv/ubuntu/bionic/llvm-riscv.tar.bz2.parta$x + wget $REPOSITORY/llvm-vortex/ubuntu/bionic/llvm-vortex1.tar.bz2.parta$x done - cat llvm-riscv.tar.bz2.parta* > llvm-riscv.tar.bz2 - tar -xvf llvm-riscv.tar.bz2 - rm -f llvm-riscv.tar.bz2* + cat llvm-vortex1.tar.bz2.parta* > llvm-vortex1.tar.bz2 + tar -xvf llvm-vortex1.tar.bz2 + rm -f llvm-vortex1.tar.bz2* cp -r llvm-riscv $DESTDIR rm -rf llvm-riscv } pocl() { - wget $REPOSITORY/pocl/ubuntu/bionic/pocl.tar.bz2 - tar -xvf pocl.tar.bz2 - rm -f pocl.tar.bz2 + wget $REPOSITORY/pocl/ubuntu/bionic/pocl1.tar.bz2 + tar -xvf pocl1.tar.bz2 + rm -f pocl1.tar.bz2 cp -r pocl $DESTDIR rm -rf pocl } diff --git a/sim/rtlsim/Makefile b/sim/rtlsim/Makefile index 3a48625b..2f7bb8f7 100644 --- a/sim/rtlsim/Makefile +++ b/sim/rtlsim/Makefile @@ -44,7 +44,7 @@ endif VL_FLAGS = --exe --cc $(TOP) --top-module $(TOP) VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic -VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO +VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO -Wno-EOFNEWLINE VL_FLAGS += --x-initial unique --x-assign unique VL_FLAGS += verilator.vlt VL_FLAGS += $(RTL_INCLUDE) diff --git a/sim/rtlsim/processor.cpp b/sim/rtlsim/processor.cpp index 0838c0ad..60e68eff 100644 --- a/sim/rtlsim/processor.cpp +++ b/sim/rtlsim/processor.cpp @@ -462,7 +462,7 @@ private: } printf("\n"); */ - memcpy((uint8_t*)device_->mem_rsp_data, mem_req->block.data(), MEM_BLOCK_SIZE); + memcpy(device_->mem_rsp_data.data(), mem_req->block.data(), MEM_BLOCK_SIZE); device_->mem_rsp_tag = mem_req->tag; pending_mem_reqs_.erase(mem_rsp_it); mem_rd_rsp_active_ = true; @@ -478,7 +478,7 @@ private: if (device_->mem_req_rw) { // process writes uint64_t byteen = device_->mem_req_byteen; - uint8_t* data = (uint8_t*)(device_->mem_req_data); + uint8_t* data = (uint8_t*)device_->mem_req_data.data(); // check console output if (byte_addr >= IO_COUT_ADDR diff --git a/sim/vlsim/Makefile b/sim/vlsim/Makefile index 3358c664..7565aaab 100644 --- a/sim/vlsim/Makefile +++ b/sim/vlsim/Makefile @@ -41,7 +41,7 @@ TOP = vortex_afu_shim VL_FLAGS = --exe --cc $(TOP) --top-module $(TOP) VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic -VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO +VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO -Wno-EOFNEWLINE VL_FLAGS += --x-initial unique --x-assign unique VL_FLAGS += verilator.vlt VL_FLAGS += $(RTL_INCLUDE) diff --git a/sim/vlsim/opae_sim.cpp b/sim/vlsim/opae_sim.cpp index 17bcbb2e..de4bf191 100644 --- a/sim/vlsim/opae_sim.cpp +++ b/sim/vlsim/opae_sim.cpp @@ -399,7 +399,7 @@ private: unsigned byte_addr = device_->avs_address[b] * MEM_BLOCK_SIZE; if (device_->avs_write[b]) { uint64_t byteen = device_->avs_byteenable[b]; - uint8_t* data = (uint8_t*)(device_->avs_writedata[b]); + uint8_t* data = (uint8_t*)device_->avs_writedata[b].data(); for (int i = 0; i < MEM_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { (*ram_)[byte_addr + i] = data[i]; From 1243848963b489eb3c91edcc418e47ac03e4b7d8 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 15 May 2023 19:13:45 -0400 Subject: [PATCH 2/5] minor update --- ci/toolchain_install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci/toolchain_install.sh b/ci/toolchain_install.sh index 6422300d..b83f15ca 100755 --- a/ci/toolchain_install.sh +++ b/ci/toolchain_install.sh @@ -9,7 +9,7 @@ DESTDIR="${DESTDIR:=/opt}" riscv() { - for x in {a..o} + for x in {a..j} do wget $REPOSITORY/riscv-gnu-toolchain/ubuntu/bionic/riscv-gnu-toolchain.tar.bz2.parta$x done From 1136c664f1090c5f89c28e98a75d5cc3f5e2867d Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 15 May 2023 19:51:20 -0400 Subject: [PATCH 3/5] minor update --- ci/travis_run.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/ci/travis_run.py b/ci/travis_run.py index b3a3626d..8b524314 100755 --- a/ci/travis_run.py +++ b/ci/travis_run.py @@ -23,12 +23,14 @@ def execute(command): process = subprocess.Popen(command, stdout=subprocess.PIPE) while True: output = process.stdout.readline() - if output == '' and process.poll() is not None: - break if output: - print output.strip() - sys.stdout.flush() - return process.returncode + line = output.decode('ascii').rstrip() + print(">>> " + line) + process.stdout.flush() + ret = process.poll() + if ret is not None: + return ret + return -1 def main(argv): From b9cda8fca7546257782067c276adf6b695c60371 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 15 May 2023 20:19:14 -0400 Subject: [PATCH 4/5] minor update --- tests/regression/diverge/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/regression/diverge/Makefile b/tests/regression/diverge/Makefile index 4ff79154..b78019fc 100644 --- a/tests/regression/diverge/Makefile +++ b/tests/regression/diverge/Makefile @@ -11,7 +11,7 @@ VX_CXX = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-g++ VX_DP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objdump VX_CP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objcopy -VX_CFLAGS += -march=rv32imf -mabi=ilp32f -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections +VX_CFLAGS += -march=rv32imf -mabi=ilp32f -O1 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections VX_CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw VX_LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link$(XLEN).ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a From d69a64c32ceaee5afdc6da3d74a5b6dcbb2fe5b5 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 16 May 2023 04:59:01 -0400 Subject: [PATCH 5/5] minor update --- hw/rtl/cache/VX_core_req_bank_sel.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/rtl/cache/VX_core_req_bank_sel.sv b/hw/rtl/cache/VX_core_req_bank_sel.sv index 1197edfb..0e5f3393 100644 --- a/hw/rtl/cache/VX_core_req_bank_sel.sv +++ b/hw/rtl/cache/VX_core_req_bank_sel.sv @@ -93,6 +93,7 @@ module VX_core_req_bank_sel #( always @(*) begin per_bank_line_addr_r = 'x; + per_bank_rw_r = 'x; for (integer i = NUM_REQS-1; i >= 0; --i) begin if (core_req_valid[i]) begin per_bank_line_addr_r[core_req_bid[i]] = core_req_line_addr[i];