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fixed Modelsim build errors

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This commit is contained in:
Blaise Tine
2020-03-26 03:54:23 -04:00
parent 07c52d8729
commit 8aa2d74714
4 changed files with 27 additions and 39 deletions
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50
rtl/VX_cache/VX_bank.v
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@@ -242,6 +242,9 @@ module VX_bank
wire[31:0] miss_add_pc; wire[31:0] miss_add_pc;
wire[31:0] addr_st2;
wire is_fill_st2;
VX_cache_miss_resrv #( VX_cache_miss_resrv #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
@@ -298,6 +301,11 @@ module VX_bank
wire stall_bank_pipe; wire stall_bank_pipe;
reg is_fill_in_pipe; reg is_fill_in_pipe;
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire is_fill_st1 [STAGE_1_CYCLES-1:0];
wire going_to_write_st1[STAGE_1_CYCLES-1:0];
wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
reg[16:0] p_stage; reg[16:0] p_stage;
always @(*) begin always @(*) begin
is_fill_in_pipe = 0; is_fill_in_pipe = 0;
@@ -316,7 +324,6 @@ module VX_bank
assign reqq_pop = !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe; assign reqq_pop = !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe;
assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0; assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0;
integer st1_cycle; integer st1_cycle;
always @(*) begin always @(*) begin
@@ -334,9 +341,6 @@ module VX_bank
end end
end end
wire qual_is_fill_st0; wire qual_is_fill_st0;
wire qual_valid_st0; wire qual_valid_st0;
wire [31:0] qual_addr_st0; wire [31:0] qual_addr_st0;
@@ -347,12 +351,8 @@ module VX_bank
wire qual_is_snp; wire qual_is_snp;
wire [31:0] qual_pc_st0; wire [31:0] qual_pc_st0;
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire going_to_write_st1[STAGE_1_CYCLES-1:0];
wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0]; wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire is_fill_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0]; wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
wire is_snp_st1 [STAGE_1_CYCLES-1:0]; wire is_snp_st1 [STAGE_1_CYCLES-1:0];
wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0]; wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0];
@@ -493,16 +493,14 @@ module VX_bank
wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1]; wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
wire valid_st2; wire valid_st2;
wire[31:0] addr_st2;
wire[`WORD_SIZE_RNG] writeword_st2; wire[`WORD_SIZE_RNG] writeword_st2;
wire[`WORD_SIZE_RNG] readword_st2; wire[`WORD_SIZE_RNG] readword_st2;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st2; wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st2;
wire miss_st2; wire miss_st2;
wire dirty_st2; wire dirty_st2;
wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2; wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
wire[`TAG_SELECT_SIZE_RNG] readtag_st2; wire[`TAG_SELECT_SIZE_RNG] readtag_st2;
wire is_fill_st2;
wire fill_saw_dirty_st2; wire fill_saw_dirty_st2;
wire is_snp_st2; wire is_snp_st2;
wire [31:0] pc_st2; wire [31:0] pc_st2;
@@ -517,6 +515,10 @@ module VX_bank
.out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 }) .out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 })
); );
wire cwbq_full;
wire dwbq_full;
wire ffsq_full;
wire invalidate_fill;
// Enqueue to miss reserv if it's a valid miss // Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full)); assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full));
@@ -534,8 +536,7 @@ module VX_bank
wire [1:0] cwbq_wb = miss_add_wb; wire [1:0] cwbq_wb = miss_add_wb;
wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num; wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num;
wire [31:0] cwbq_pc = pc_st2; wire [31:0] cwbq_pc = pc_st2;
wire cwbq_full;
wire cwbq_empty; wire cwbq_empty;
assign bank_wb_valid = !cwbq_empty; assign bank_wb_valid = !cwbq_empty;
VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue( VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue(
@@ -556,11 +557,8 @@ module VX_bank
wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK; wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2; wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2;
wire dwbq_empty; wire dwbq_empty;
wire dwbq_full;
wire possible_fill = valid_st2 && miss_st2;
wire invalidate_fill;
wire possible_fill = valid_st2 && miss_st2;
wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK; wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK;
VX_fill_invalidator #( VX_fill_invalidator #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
@@ -611,8 +609,7 @@ module VX_bank
.full (dwbq_full) .full (dwbq_full)
); );
wire snp_fwd_push; wire snp_fwd_push;
wire ffsq_full;
wire ffsq_empty; wire ffsq_empty;
assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
@@ -628,13 +625,6 @@ module VX_bank
.full (ffsq_full) .full (ffsq_full)
); );
assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full); assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full);
endmodule : VX_bank endmodule : VX_bank

1
rtl/VX_cache/VX_snp_fwd_arb.v
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@@ -1,3 +1,4 @@
`include "VX_cache_config.v"
module VX_snp_fwd_arb module VX_snp_fwd_arb
#( #(

13
rtl/VX_cache/VX_tag_data_access.v
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@@ -93,6 +93,7 @@ module VX_tag_data_access
wire[`DBANK_LINE_SIZE_RNG][3:0] use_write_enable; wire[`DBANK_LINE_SIZE_RNG][3:0] use_write_enable;
wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data; wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data;
wire sw, sb, sh;
wire real_writefill = writefill_st1e && ((valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e))); wire real_writefill = writefill_st1e && ((valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)));
@@ -230,9 +231,9 @@ module VX_tag_data_access
/////////////////////// STORE LOGIC /////////////////// /////////////////////// STORE LOGIC ///////////////////
wire sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE); assign sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE);
wire sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE); assign sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE);
wire sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE); assign sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE);
wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000))); wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
@@ -279,8 +280,4 @@ module VX_tag_data_access
assign fill_saw_dirty_st1e = force_write && dirty_st1e && miss_st1e; assign fill_saw_dirty_st1e = force_write && dirty_st1e && miss_st1e;
assign invalidate_line = is_snp_st1e && !miss_st1e; assign invalidate_line = is_snp_st1e && !miss_st1e;
endmodule endmodule

2
rtl/VX_define.v
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@@ -127,7 +127,7 @@
`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
`define SINGLE_CORE_BENCH //`define SINGLE_CORE_BENCH
`define GLOBAL_BLOCK_SIZE_BYTES 16 `define GLOBAL_BLOCK_SIZE_BYTES 16