tensor: Add ready signal to enforce 1 warp occupancy

Currently disabled as the timing behavior is already ~accurate

hw/rtl/fpu/VX_tensor_dpu.sv

@@ -11,6 +11,7 @@ module VX_tensor_dpu #(
     input stall,
 
     input valid_in,
+    output ready_in,
     input [3:0][1:0][31:0] A_tile,
     input [1:0][3:0][31:0] B_tile,
     input [3:0][3:0][31:0] C_tile,
@@ -24,12 +25,20 @@ module VX_tensor_dpu #(
         dpi_hmma(valid_in, A_tile, B_tile, C_tile, result_hmma);
     end
 
+    logic ready_reg;
     always @(posedge clk) begin
-        if (~reset && valid_in) begin
+        if (reset) begin
+            ready_reg <= '1;
+        end else if (valid_in) begin
+            ready_reg <= '0;
             dpi_print_results(int'(ISW), int'(OCTET), A_tile, B_tile, C_tile, result_hmma);
+        end else if (valid_out) begin
+            ready_reg <= '1;
         end
     end
-    
+
+    // ready as soon as valid_out
+    assign ready_in = ready_reg || valid_out;
 
     VX_shift_register #(
         .DATAW  (1 + $bits(D_tile)),