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This commit is contained in:
felsabbagh3
2019-10-25 04:01:23 -04:00
parent 01efe02e8b
commit 89d0390965
10 changed files with 106 additions and 37 deletions
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24
kernel/vortex_test.dump
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@@ -1604,7 +1604,7 @@ Disassembly of section .text:
80001778: 00178793 addi a5,a5,1 80001778: 00178793 addi a5,a5,1
8000177c: fef42623 sw a5,-20(s0) 8000177c: fef42623 sw a5,-20(s0)
80001780: fec42703 lw a4,-20(s0) 80001780: fec42703 lw a4,-20(s0)
80001784: 00300793 li a5,3 80001784: 0ff00793 li a5,255
80001788: fae7dae3 bge a5,a4,8000173c <initialize_mats+0x14> 80001788: fae7dae3 bge a5,a4,8000173c <initialize_mats+0x14>
8000178c: 00000013 nop 8000178c: 00000013 nop
80001790: 01c12403 lw s0,28(sp) 80001790: 01c12403 lw s0,28(sp)
@@ -1625,7 +1625,7 @@ Disassembly of section .text:
800017c4: fec42783 lw a5,-20(s0) 800017c4: fec42783 lw a5,-20(s0)
800017c8: 00078e63 beqz a5,800017e4 <print_matrix+0x48> 800017c8: 00078e63 beqz a5,800017e4 <print_matrix+0x48>
800017cc: fec42783 lw a5,-20(s0) 800017cc: fec42783 lw a5,-20(s0)
800017d0: 0017f793 andi a5,a5,1 800017d0: 00f7f793 andi a5,a5,15
800017d4: 00079863 bnez a5,800017e4 <print_matrix+0x48> 800017d4: 00079863 bnez a5,800017e4 <print_matrix+0x48>
800017d8: 810007b7 lui a5,0x81000 800017d8: 810007b7 lui a5,0x81000
800017dc: 13c78513 addi a0,a5,316 # 8100013c <barrier_bool+0xfffd6e74> 800017dc: 13c78513 addi a0,a5,316 # 8100013c <barrier_bool+0xfffd6e74>
@@ -1644,7 +1644,7 @@ Disassembly of section .text:
80001810: 00178793 addi a5,a5,1 80001810: 00178793 addi a5,a5,1
80001814: fef42623 sw a5,-20(s0) 80001814: fef42623 sw a5,-20(s0)
80001818: fec42703 lw a4,-20(s0) 80001818: fec42703 lw a4,-20(s0)
8000181c: 00300793 li a5,3 8000181c: 0ff00793 li a5,255
80001820: fae7d2e3 bge a5,a4,800017c4 <print_matrix+0x28> 80001820: fae7d2e3 bge a5,a4,800017c4 <print_matrix+0x28>
80001824: 810007b7 lui a5,0x81000 80001824: 810007b7 lui a5,0x81000
80001828: 14478513 addi a0,a5,324 # 81000144 <barrier_bool+0xfffd6e7c> 80001828: 14478513 addi a0,a5,324 # 81000144 <barrier_bool+0xfffd6e7c>
@@ -1660,14 +1660,16 @@ Disassembly of section .text:
80001848: 00112623 sw ra,12(sp) 80001848: 00112623 sw ra,12(sp)
8000184c: 00812423 sw s0,8(sp) 8000184c: 00812423 sw s0,8(sp)
80001850: 01010413 addi s0,sp,16 80001850: 01010413 addi s0,sp,16
80001854: 00b00513 li a0,11 80001854: ed5ff0ef jal ra,80001728 <initialize_mats>
80001858: fa5fe0ef jal ra,800007fc <vx_print_hex> 80001858: 810267b7 lui a5,0x81026
8000185c: 00000793 li a5,0 8000185c: 22078513 addi a0,a5,544 # 81026220 <barrier_bool+0xffffcf58>
80001860: 00078513 mv a0,a5 80001860: f3dff0ef jal ra,8000179c <print_matrix>
80001864: 00c12083 lw ra,12(sp) 80001864: 00000793 li a5,0
80001868: 00812403 lw s0,8(sp) 80001868: 00078513 mv a0,a5
8000186c: 01010113 addi sp,sp,16 8000186c: 00c12083 lw ra,12(sp)
80001870: 00008067 ret 80001870: 00812403 lw s0,8(sp)
80001874: 01010113 addi sp,sp,16
80001878: 00008067 ret
Disassembly of section .rodata: Disassembly of section .rodata:

BIN
kernel/vortex_test.elf
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Binary file not shown.

12
kernel/vortex_test.hex
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@@ -375,22 +375,22 @@
:101750001307300023A0E700B77702810327C4FEF8 :101750001307300023A0E700B77702810327C4FEF8
:101760001317270093870722B307F70013072000FA :101760001317270093870722B307F70013072000FA
:1017700023A0E7008327C4FE938717002326F4FEE7 :1017700023A0E7008327C4FE938717002326F4FEE7
:101780000327C4FE93073000E3DAE7FA13000000F2 :101780000327C4FE9307F00FE3DAE7FA1300000023
:101790000324C1011301010267800000130101FD50 :101790000324C1011301010267800000130101FD50
:1017A000232611022324810213040103232EA4FC07 :1017A000232611022324810213040103232EA4FC07
:1017B000B707008113858711EFF08F80232604FE81 :1017B000B707008113858711EFF08F80232604FE81
:1017C0006F0080058327C4FE638E07008327C4FE55 :1017C0006F0080058327C4FE638E07008327C4FE55
:1017D00093F7170063980700B70700811385C713B5 :1017D00093F7F70063980700B70700811385C713D5
:1017E000EFE01FFE8327C4FE939727000327C4FD65 :1017E000EFE01FFE8327C4FE939727000327C4FD65
:1017F000B307F70083A7070013850700EFF00F80FA :1017F000B307F70083A7070013850700EFF00F80FA
:10180000B707008113850714EFE09FFB8327C4FE11 :10180000B707008113850714EFE09FFB8327C4FE11
:10181000938717002326F4FE0327C4FE93073000A6 :10181000938717002326F4FE0327C4FE9307F00FD7
:10182000E3D2E7FAB707008113854714EFE05FF9C9 :10182000E3D2E7FAB707008113854714EFE05FF9C9
:10183000130000008320C10203248102130101036D :10183000130000008320C10203248102130101036D
:1018400067800000130101FF23261100232481007B :1018400067800000130101FF23261100232481007B
:10185000130401011305B000EFE05FFA93070000E5 :1018500013040101EFF05FEDB767028113850722E2
:10186000138507008320C1000324810013010101B7 :10186000EFF0DFF393070000138507008320C1002A
:04187000678000008D :0C187000032481001301010167800000C7
:02000004810079 :02000004810079
:10000000300000003100000032000000330000002A :10000000300000003100000032000000330000002A
:10001000340000003500000036000000370000000A :10001000340000003500000036000000370000000A

12
kernel/vx_main.c
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@@ -7,10 +7,10 @@ unsigned z[1024] = {0};
unsigned temp = 6; unsigned temp = 6;
#define MAT_DIM 2 #define MAT_DIM 16
#define NUM_COLS 2 #define NUM_COLS 16
#define NUM_ROWS 2 #define NUM_ROWS 16
double sc_time_stamp() double sc_time_stamp()
{ {
@@ -43,17 +43,17 @@ int main()
// unsigned f = temp; // unsigned f = temp;
vx_print_hex(11); // vx_print_hex(11);
// vx_printc(0, 'a'); // vx_printc(0, 'a');
// initialize_mats(); initialize_mats();
// matrix multiplication // matrix multiplication
// vx_sq_mat_mult(x, y, z, MAT_DIM); // vx_sq_mat_mult(x, y, z, MAT_DIM);
// vx_print_str("\n\nMatrix multiplication\n"); // vx_print_str("\n\nMatrix multiplication\n");
// print_matrix(z); // print_matrix(z);
// print_matrix(x); print_matrix(x);
// // matrix addition // // matrix addition
// vx_mat_add(x, y, z, NUM_ROWS, NUM_COLS); // vx_mat_add(x, y, z, NUM_ROWS, NUM_COLS);

2
rtl/VX_dmem_controller.v
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@@ -57,6 +57,8 @@ module VX_dmem_controller (
.i_p_addr (cache_driver_in_address), .i_p_addr (cache_driver_in_address),
.i_p_writedata (cache_driver_in_data), .i_p_writedata (cache_driver_in_data),
.i_p_read_or_write (read_or_write), .i_p_read_or_write (read_or_write),
.i_p_mem_read (cache_driver_in_mem_read),
.i_p_mem_write (cache_driver_in_mem_write),
.o_p_readdata (cache_driver_out_data), .o_p_readdata (cache_driver_out_data),
.o_p_delay (cache_delay), .o_p_delay (cache_delay),
.o_m_evict_addr (VX_dram_req_rsp.o_m_evict_addr), .o_m_evict_addr (VX_dram_req_rsp.o_m_evict_addr),

63
rtl/cache/VX_Cache_Bank.v vendored
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@@ -16,6 +16,8 @@ module VX_Cache_Bank
clk, clk,
state, state,
read_or_write, // Read = 0 | Write = 1 read_or_write, // Read = 0 | Write = 1
i_p_mem_read,
i_p_mem_write,
valid_in, valid_in,
//write_from_mem, //write_from_mem,
actual_index, actual_index,
@@ -24,6 +26,7 @@ module VX_Cache_Bank
writedata, writedata,
fetched_writedata, fetched_writedata,
byte_select,
readdata, readdata,
hit, hit,
@@ -57,8 +60,9 @@ module VX_Cache_Bank
input wire read_or_write; // Specifies if it is a read or write operation input wire read_or_write; // Specifies if it is a read or write operation
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata; input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write;
input wire[1:0] byte_select;
// Outputs // Outputs
// Normal shit // Normal shit
@@ -94,18 +98,67 @@ module VX_Cache_Bank
assign eviction_tag = tag_use; assign eviction_tag = tag_use;
assign access = (state == CACHE_IDLE) && valid_in; assign access = (state == CACHE_IDLE) && valid_in;
assign write_from_mem = (state == RECIV_MEM_RSP); assign write_from_mem = (state == RECIV_MEM_RSP);
assign readdata = (access) ? data_use[block_offset] : 32'b0; // Fix with actual data
assign hit = (access && (tag_use == o_tag) && valid_use); assign hit = (access && (tag_use == o_tag) && valid_use);
//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data //assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data
wire[`NUM_WORDS_PER_BLOCK-1:0] we;
wire lb = (i_p_mem_read == `LB_MEM_READ);
wire lh = (i_p_mem_read == `LH_MEM_READ);
wire lhu = (i_p_mem_read == `LHU_MEM_READ);
wire lbu = (i_p_mem_read == `LBU_MEM_READ);
wire sw = (i_p_mem_write == `SW_MEM_WRITE);
wire sb = (i_p_mem_write == `SB_MEM_WRITE);
wire sh = (i_p_mem_write == `SH_MEM_WRITE);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire[31:0] data_unQual = b0 ? (data_use[block_offset] ) :
b1 ? (data_use[block_offset] >> 8) :
b2 ? (data_use[block_offset] >> 16) :
(data_use[block_offset] >> 24);
wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
wire[31:0] lbu_data = (data_unQual & 32'hFF);
wire[31:0] lhu_data = (data_unQual & 32'hFFFF);
wire[31:0] lw_data = (data_unQual);
wire[31:0] data_Qual = lb ? lb_data :
lh ? lh_data :
lhu ? lhu_data :
lbu ? lbu_data :
lw_data;
assign readdata = (access) ? data_Qual : 32'b0; // Fix with actual data
wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write; wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g; genvar g;
for (g = 0; g < `NUM_WORDS_PER_BLOCK; g = g + 1) begin for (g = 0; g < `NUM_WORDS_PER_BLOCK; g = g + 1) begin
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss); wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
assign we[g] = (write_from_mem) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
// assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
assign data_write[g] = write_from_mem ? fetched_writedata[g] : writedata; assign data_write[g] = write_from_mem ? fetched_writedata[g] : writedata;
end end

12
rtl/cache/VX_cache_data.v vendored
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@@ -7,7 +7,7 @@ module VX_cache_data (
// Addr // Addr
input wire[$clog2(NUMBER_INDEXES)-1:0] addr, input wire[$clog2(NUMBER_INDEXES)-1:0] addr,
// WE // WE
input wire[`NUM_WORDS_PER_BLOCK-1:0] we, input wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict, input wire evict,
// Data // Data
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
@@ -33,7 +33,7 @@ module VX_cache_data (
`ifndef SYN `ifndef SYN
// (3:0) 4 bytes // (3:0) 4 bytes
reg[`NUM_WORDS_PER_BLOCK-1:0][31:0] data[NUMBER_INDEXES-1:0]; // Actual Data reg[`NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUMBER_INDEXES-1:0]; // Actual Data
reg[16:0] tag[NUMBER_INDEXES-1:0]; reg[16:0] tag[NUMBER_INDEXES-1:0];
reg valid[NUMBER_INDEXES-1:0]; reg valid[NUMBER_INDEXES-1:0];
reg dirty[NUMBER_INDEXES-1:0]; reg dirty[NUMBER_INDEXES-1:0];
@@ -46,14 +46,18 @@ module VX_cache_data (
assign dirty_use = dirty[addr]; assign dirty_use = dirty[addr];
integer f; genvar f;
genvar z;
always @(posedge clk) begin : dirty_update always @(posedge clk) begin : dirty_update
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
end end
always @(posedge clk) begin : data_update always @(posedge clk) begin : data_update
for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f]) data[addr][f] <= data_write[f]; if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
if (we[f][3]) data[addr][f][3] <= data_write[f][31:24];
end end
end end

8
rtl/cache/VX_d_cache.v vendored
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@@ -20,6 +20,8 @@ module VX_d_cache(clk,
//i_p_byte_en, //i_p_byte_en,
i_p_writedata, i_p_writedata,
i_p_read_or_write, // 0 = Read | 1 = Write i_p_read_or_write, // 0 = Read | 1 = Write
i_p_mem_read,
i_p_mem_write,
i_p_valid, i_p_valid,
//i_p_write, //i_p_write,
o_p_readdata, o_p_readdata,
@@ -60,6 +62,8 @@ module VX_d_cache(clk,
input wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; input wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire i_m_ready; input wire i_m_ready;
input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write;
// Buffer for final data // Buffer for final data
@@ -229,6 +233,7 @@ module VX_d_cache(clk,
wire[7:0] cache_index = bank_addr[14:7]; wire[7:0] cache_index = bank_addr[14:7];
wire[16:0] cache_tag = bank_addr[31:15]; wire[16:0] cache_tag = bank_addr[31:15];
wire[1:0] cache_offset = bank_addr[6:5]; wire[1:0] cache_offset = bank_addr[6:5];
wire[1:0] byte_select = bank_addr[1:0];
wire normal_valid_in = valid_per_bank[bank_id]; wire normal_valid_in = valid_per_bank[bank_id];
wire use_valid_in = ((state == RECIV_MEM_RSP) && i_m_ready) ? 1'b1 : wire use_valid_in = ((state == RECIV_MEM_RSP) && i_m_ready) ? 1'b1 :
@@ -245,6 +250,9 @@ module VX_d_cache(clk,
.block_offset (cache_offset), .block_offset (cache_offset),
.writedata (i_p_writedata[send_index_to_bank[bank_id]]), .writedata (i_p_writedata[send_index_to_bank[bank_id]]),
.read_or_write (i_p_read_or_write), .read_or_write (i_p_read_or_write),
.i_p_mem_read (i_p_mem_read),
.i_p_mem_write (i_p_mem_write),
.byte_select (byte_select),
.hit (hit_per_bank[bank_id]), .hit (hit_per_bank[bank_id]),
.readdata (readdata_per_bank[bank_id]), // Data read .readdata (readdata_per_bank[bank_id]), // Data read
.eviction_addr (eviction_addr_per_bank[bank_id]), .eviction_addr (eviction_addr_per_bank[bank_id]),

8
rtl/results.txt
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@@ -1,7 +1,7 @@
# Dynamic Instructions: 4139 # Dynamic Instructions: 51711
# of total cycles: 4156 # of total cycles: 51728
# of forwarding stalls: 0 # of forwarding stalls: 0
# of branch stalls: 0 # of branch stalls: 0
# CPI: 1.00411 # CPI: 1.00033
# time to simulate: 6.95312e-310 milliseconds # time to simulate: 0 milliseconds
# GRADE: Failed on test: 4294967295 # GRADE: Failed on test: 4294967295

2
rtl/simulate/tb_debug.h
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@@ -1 +1 @@
#define VCD_OUTPUT #define VCD_OFF