CACHE FINALLY WORKING
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8
rtl/cache/VX_d_cache.v
vendored
8
rtl/cache/VX_d_cache.v
vendored
@@ -20,6 +20,8 @@ module VX_d_cache(clk,
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//i_p_byte_en,
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i_p_writedata,
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i_p_read_or_write, // 0 = Read | 1 = Write
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i_p_mem_read,
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i_p_mem_write,
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i_p_valid,
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//i_p_write,
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o_p_readdata,
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@@ -60,6 +62,8 @@ module VX_d_cache(clk,
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input wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
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input wire i_m_ready;
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input wire[2:0] i_p_mem_read;
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input wire[2:0] i_p_mem_write;
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// Buffer for final data
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@@ -229,6 +233,7 @@ module VX_d_cache(clk,
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wire[7:0] cache_index = bank_addr[14:7];
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wire[16:0] cache_tag = bank_addr[31:15];
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wire[1:0] cache_offset = bank_addr[6:5];
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wire[1:0] byte_select = bank_addr[1:0];
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wire normal_valid_in = valid_per_bank[bank_id];
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wire use_valid_in = ((state == RECIV_MEM_RSP) && i_m_ready) ? 1'b1 :
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@@ -245,6 +250,9 @@ module VX_d_cache(clk,
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.block_offset (cache_offset),
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.writedata (i_p_writedata[send_index_to_bank[bank_id]]),
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.read_or_write (i_p_read_or_write),
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.i_p_mem_read (i_p_mem_read),
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.i_p_mem_write (i_p_mem_write),
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.byte_select (byte_select),
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.hit (hit_per_bank[bank_id]),
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.readdata (readdata_per_bank[bank_id]), // Data read
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.eviction_addr (eviction_addr_per_bank[bank_id]),
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