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CACHE FINALLY WORKING

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This commit is contained in:
felsabbagh3
2019-10-25 04:01:23 -04:00
parent 01efe02e8b
commit 89d0390965
10 changed files with 106 additions and 37 deletions
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63
rtl/cache/VX_Cache_Bank.v vendored
View File

@@ -16,6 +16,8 @@ module VX_Cache_Bank
clk,
state,
read_or_write, // Read = 0 | Write = 1
i_p_mem_read,
i_p_mem_write,
valid_in,
//write_from_mem,
actual_index,
@@ -24,6 +26,7 @@ module VX_Cache_Bank
writedata,
fetched_writedata,
byte_select,
readdata,
hit,
@@ -57,8 +60,9 @@ module VX_Cache_Bank
input wire read_or_write; // Specifies if it is a read or write operation
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write;
input wire[1:0] byte_select;
// Outputs
// Normal shit
@@ -94,18 +98,67 @@ module VX_Cache_Bank
assign eviction_tag = tag_use;
assign access = (state == CACHE_IDLE) && valid_in;
assign write_from_mem = (state == RECIV_MEM_RSP);
assign readdata = (access) ? data_use[block_offset] : 32'b0; // Fix with actual data
assign hit = (access && (tag_use == o_tag) && valid_use);
//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data
wire[`NUM_WORDS_PER_BLOCK-1:0] we;
wire lb = (i_p_mem_read == `LB_MEM_READ);
wire lh = (i_p_mem_read == `LH_MEM_READ);
wire lhu = (i_p_mem_read == `LHU_MEM_READ);
wire lbu = (i_p_mem_read == `LBU_MEM_READ);
wire sw = (i_p_mem_write == `SW_MEM_WRITE);
wire sb = (i_p_mem_write == `SB_MEM_WRITE);
wire sh = (i_p_mem_write == `SH_MEM_WRITE);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire[31:0] data_unQual = b0 ? (data_use[block_offset] ) :
b1 ? (data_use[block_offset] >> 8) :
b2 ? (data_use[block_offset] >> 16) :
(data_use[block_offset] >> 24);
wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
wire[31:0] lbu_data = (data_unQual & 32'hFF);
wire[31:0] lhu_data = (data_unQual & 32'hFFFF);
wire[31:0] lw_data = (data_unQual);
wire[31:0] data_Qual = lb ? lb_data :
lh ? lh_data :
lhu ? lhu_data :
lbu ? lbu_data :
lw_data;
assign readdata = (access) ? data_Qual : 32'b0; // Fix with actual data
wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g;
for (g = 0; g < `NUM_WORDS_PER_BLOCK; g = g + 1) begin
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
assign we[g] = (write_from_mem) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
// assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
assign data_write[g] = write_from_mem ? fetched_writedata[g] : writedata;
end

12
rtl/cache/VX_cache_data.v vendored
View File

@@ -7,7 +7,7 @@ module VX_cache_data (
// Addr
input wire[$clog2(NUMBER_INDEXES)-1:0] addr,
// WE
input wire[`NUM_WORDS_PER_BLOCK-1:0] we,
input wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict,
// Data
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
@@ -33,7 +33,7 @@ module VX_cache_data (
`ifndef SYN
// (3:0) 4 bytes
reg[`NUM_WORDS_PER_BLOCK-1:0][31:0] data[NUMBER_INDEXES-1:0]; // Actual Data
reg[`NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUMBER_INDEXES-1:0]; // Actual Data
reg[16:0] tag[NUMBER_INDEXES-1:0];
reg valid[NUMBER_INDEXES-1:0];
reg dirty[NUMBER_INDEXES-1:0];
@@ -46,14 +46,18 @@ module VX_cache_data (
assign dirty_use = dirty[addr];
integer f;
genvar f;
genvar z;
always @(posedge clk) begin : dirty_update
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
end
always @(posedge clk) begin : data_update
for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f]) data[addr][f] <= data_write[f];
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
if (we[f][3]) data[addr][f][3] <= data_write[f][31:24];
end
end

8
rtl/cache/VX_d_cache.v vendored
View File

@@ -20,6 +20,8 @@ module VX_d_cache(clk,
//i_p_byte_en,
i_p_writedata,
i_p_read_or_write, // 0 = Read | 1 = Write
i_p_mem_read,
i_p_mem_write,
i_p_valid,
//i_p_write,
o_p_readdata,
@@ -60,6 +62,8 @@ module VX_d_cache(clk,
input wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire i_m_ready;
input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write;
// Buffer for final data
@@ -229,6 +233,7 @@ module VX_d_cache(clk,
wire[7:0] cache_index = bank_addr[14:7];
wire[16:0] cache_tag = bank_addr[31:15];
wire[1:0] cache_offset = bank_addr[6:5];
wire[1:0] byte_select = bank_addr[1:0];
wire normal_valid_in = valid_per_bank[bank_id];
wire use_valid_in = ((state == RECIV_MEM_RSP) && i_m_ready) ? 1'b1 :
@@ -245,6 +250,9 @@ module VX_d_cache(clk,
.block_offset (cache_offset),
.writedata (i_p_writedata[send_index_to_bank[bank_id]]),
.read_or_write (i_p_read_or_write),
.i_p_mem_read (i_p_mem_read),
.i_p_mem_write (i_p_mem_write),
.byte_select (byte_select),
.hit (hit_per_bank[bank_id]),
.readdata (readdata_per_bank[bank_id]), // Data read
.eviction_addr (eviction_addr_per_bank[bank_id]),