floating point support fixes

driver/rtlsim/Makefile

@@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO
 #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
 CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
 
-DEBUG=1
+#DEBUG=1
 #AFU=1
 
 CFLAGS += -fPIC
@@ -35,11 +35,13 @@ TOP = Vortex
 
 SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
 
-RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache
+FPU_INCLUDE = -I../../hw/rtl/fp_cores/fpnew/src/common_cells/include -I../../hw/rtl/fp_cores/fpnew/src/common_cells/src -I../../hw/rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I../../hw/rtl/fp_cores/fpnew/src 
+RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache $(FPU_INCLUDE)
 
 VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
 VL_FLAGS += -Wno-DECLFILENAME
 VL_FLAGS += --x-initial unique --x-assign unique
+VL_FLAGS += verilator.vlt
 
 # Enable Verilator multithreaded simulation
 #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

driver/rtlsim/simulator.cpp

@@ -1,71 +0,0 @@
-#include "simulator.h"
-#include <iostream>
-#include <fstream>
-#include <iomanip>
-
-uint64_t timestamp = 0;
-
-double sc_time_stamp() { 
-  return timestamp;
-}
-
-Simulator::Simulator() {    
-  // force random values for unitialized signals
-  const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"};
-  Verilated::commandArgs(3, args);
-
-  vortex_ = new Vvortex_afu_sim();
-
-#ifdef VCD_OUTPUT
-  Verilated::traceEverOn(true);
-  trace_ = new VerilatedVcdC;
-  trace_->set_time_unit("1ns");
-  vortex_->trace(trace_, 99);
-  trace_->open("trace.vcd");
-#endif  
-}
-
-Simulator::~Simulator() {
-#ifdef VCD_OUTPUT
-  trace_->close();
-#endif
-  delete vortex_;
-}
-
-void Simulator::reset() {     
-#ifndef NDEBUG
-  std::cout << timestamp << ": [sim] reset()" << std::endl;
-#endif 
-  vortex_->reset = 1;
-  this->step();  
-  vortex_->reset = 0;
-
-  dram_rsp_vec_.clear();
-}
-
-void Simulator::step() {
-  vortex_->clk = 0;
-  this->eval();
-
-  vortex_->clk = 1;
-  this->eval();
-
-  avs_driver();
-  ccip_driver();
-}
-
-void Simulator::eval() {
-  vortex_->eval();
-#ifdef VCD_OUTPUT
-  trace_->dump(timestamp);
-#endif
-  ++timestamp;
-}
-
-void Simulator::avs_driver() {
-  //--
-}
-
- void Simulator::ccip_driver() {
-   //--
- }

driver/rtlsim/simulator.h

@@ -1,59 +0,0 @@
-#pragma once
-
-#include "Vvortex_afu_sim.h"
-#include "Vvortex_afu_sim__Syms.h"
-#include "verilated.h"
-
-#ifdef VCD_OUTPUT
-#include <verilated_vcd_c.h>
-#endif
-
-#include <VX_config.h>
-#include "ram.h"
-
-#include <ostream>
-#include <vector>
-
-#define ENABLE_DRAM_STALLS
-#define DRAM_LATENCY 100
-#define DRAM_RQ_SIZE 16
-#define DRAM_STALLS_MODULO 16
-
-typedef struct {
-  int cycles_left;  
-  uint8_t *data;
-  unsigned tag;
-} dram_req_t;
-
-class Simulator {
-public:
-  
-  Simulator();
-  virtual ~Simulator();
-
-  void reset();
-  
-  void step();  
-
-  int mmio_read(uint64_t addr, uint64_t* value);
-
-  int mmio_write(uint64_t addr, uint64_t value);
-  
-private:  
-
-  void eval(); 
-
-  void avs_driver();
-
-  void ccip_driver(); 
-  
-  std::vector<dram_req_t> dram_rsp_vec_;
-
-  RAM ram_;
-  Vvortex_afu_sim *vortex_;
-  
-
-#ifdef VCD_OUTPUT
-  VerilatedVcdC *trace_;
-#endif
-};

driver/rtlsim/verilator.vlt

@@ -0,0 +1,9 @@
+`verilator_config
+
+lint_off -rule BLKANDNBLK -file "../../hw/rtl/fp_cores/fpnew/*"
+lint_off -rule UNOPTFLAT -file "../../hw/rtl/fp_cores/fpnew/*"
+lint_off -rule WIDTH -file "../../hw/rtl/fp_cores/fpnew/*"
+lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*"
+lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*"
+lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*"
+lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*"