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adding DEBUG MACROS

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This commit is contained in:
Blaise Tine
2020-04-19 04:59:52 -04:00
parent 9b476f1e17
commit 885869df4a
32 changed files with 84 additions and 2397 deletions
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4
driver/rtlsim/Makefile
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@@ -1,4 +1,4 @@
CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
# CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors # CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
USE_MULTICORE=1 USE_MULTICORE=1
@@ -23,7 +23,7 @@ SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/interfaces -I../../hw/rtl/cache -I../../hw/rtl/generic_cache -I../../hw/rtl/shared_memory -I../../hw/rtl/pipe_regs -I../../hw/rtl/compat RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/interfaces -I../../hw/rtl/cache -I../../hw/rtl/generic_cache -I../../hw/rtl/shared_memory -I../../hw/rtl/pipe_regs -I../../hw/rtl/compat
VL_FLAGS += --assert -Wall -Wpedantic VL_FLAGS += -DNDEBUG --assert -Wall -Wpedantic
# Enable Verilator multithreaded simulation # Enable Verilator multithreaded simulation
#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

29
hw/Makefile
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@@ -1,23 +1,20 @@
all: singlecore all: singlecore
CF += -std=c++11 -fms-extensions
VF += -compiler gcc --language 1800-2009 --assert -Wall -Wpedantic
INCLUDE = -I./rtl/ -I./rtl/shared_memory -I./rtl/cache -I./rtl/generic_cache -I./rtl/generic_cache/interfaces -I./rtl/interfaces/ -I./rtl/pipe_regs/ -I./rtl/compat/ -I./rtl/simulate INCLUDE = -I./rtl/ -I./rtl/shared_memory -I./rtl/cache -I./rtl/generic_cache -I./rtl/generic_cache/interfaces -I./rtl/interfaces/ -I./rtl/pipe_regs/ -I./rtl/compat/ -I./rtl/simulate
SINGLE_CORE = Vortex.v SINGLE_CORE = Vortex.v
MULTI_CORE = Vortex_Socket.v MULTI_CORE = Vortex_Socket.v
EXE += --exe ./simulate/testbench.cpp ./simulate/simulator.cpp SRCS += ./simulate/testbench.cpp ./simulate/simulator.cpp
VF += -compiler gcc --language 1800-2009 VF += -exe $(SRCS) $(INCLUDE)
VF += --assert -Wall -Wpedantic DBG += --trace -DVL_DEBUG=1
# LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB +=
CF += -std=c++11 -fms-extensions
DEB += --trace -DVL_DEBUG=1
MAKECPP_S += (cd obj_dir && make -j -f VVortex.mk) MAKECPP_S += (cd obj_dir && make -j -f VVortex.mk)
@@ -31,22 +28,22 @@ build_config:
./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./simulate/VX_config.h ./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./simulate/VX_config.h
gen-singlecore: build_config gen-singlecore: build_config
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' verilator $(VF) -DNDEBUG -cc $(SINGLE_CORE) -CFLAGS '$(CF) -DNDEBUG'
gen-singlecore-t: build_config gen-singlecore-t: build_config
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -O3' --threads $(THREADS) verilator $(VF) -cc $(SINGLE_CORE) -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS)
gen-singlecore-d: build_config gen-singlecore-d: build_config
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT' $(DEB) verilator $(VF) -cc $(SINGLE_CORE) -CFLAGS '$(CF) -DVCD_OUTPUT' $(DBG)
gen-multicore: build_config gen-multicore: build_config
verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE' verilator $(VF) -DNDEBUG -cc $(MULTI_CORE) -CFLAGS '$(CF) -DNDEBUG -DUSE_MULTICORE'
gen-multicore-t: build_config gen-multicore-t: build_config
verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE -O3' --threads $(THREADS) verilator $(VF) -DNDEBUG -cc $(MULTI_CORE) -CFLAGS '$(CF) -DNDEBUG -O2 -DUSE_MULTICORE' --threads $(THREADS)
gen-multicore-d: build_config gen-multicore-d: build_config
verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DUSE_MULTICORE' $(DEB) verilator $(VF) -cc $(MULTI_CORE) -CFLAGS '$(CF) -DVCD_OUTPUT -DUSE_MULTICORE' $(DBG)
singlecore: gen-singlecore singlecore: gen-singlecore
(cd obj_dir && make -j -f VVortex.mk) (cd obj_dir && make -j -f VVortex.mk)

2
hw/modelsim/Makefile
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@@ -17,11 +17,9 @@ SRC = \
../rtl/interfaces/VX_dram_req_rsp_inter.v \ ../rtl/interfaces/VX_dram_req_rsp_inter.v \
../rtl/interfaces/VX_exec_unit_req_inter.v \ ../rtl/interfaces/VX_exec_unit_req_inter.v \
../rtl/interfaces/VX_frE_to_bckE_req_inter.v \ ../rtl/interfaces/VX_frE_to_bckE_req_inter.v \
../rtl/interfaces/VX_gpr_clone_inter.v \
../rtl/interfaces/VX_gpr_data_inter.v \ ../rtl/interfaces/VX_gpr_data_inter.v \
../rtl/interfaces/VX_gpr_jal_inter.v \ ../rtl/interfaces/VX_gpr_jal_inter.v \
../rtl/interfaces/VX_gpr_read_inter.v \ ../rtl/interfaces/VX_gpr_read_inter.v \
../rtl/interfaces/VX_gpr_wspawn_inter.v \
../rtl/interfaces/VX_gpu_inst_req_inter.v \ ../rtl/interfaces/VX_gpu_inst_req_inter.v \
../rtl/interfaces/VX_icache_request_inter.v \ ../rtl/interfaces/VX_icache_request_inter.v \
../rtl/interfaces/VX_icache_response_inter.v \ ../rtl/interfaces/VX_icache_response_inter.v \

2275
hw/modelsim/modelsim.mpf
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File diff suppressed because it is too large Load Diff

2
hw/opae/sources.txt
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@@ -87,7 +87,6 @@ vortex_afu.json
../rtl/interfaces/VX_inst_meta_inter.v ../rtl/interfaces/VX_inst_meta_inter.v
../rtl/interfaces/VX_join_inter.v ../rtl/interfaces/VX_join_inter.v
../rtl/interfaces/VX_icache_response_inter.v ../rtl/interfaces/VX_icache_response_inter.v
../rtl/interfaces/VX_gpr_wspawn_inter.v
../rtl/interfaces/VX_inst_exec_wb_inter.v ../rtl/interfaces/VX_inst_exec_wb_inter.v
../rtl/interfaces/VX_gpu_dcache_dram_req_inter.v ../rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
../rtl/interfaces/VX_csr_req_inter.v ../rtl/interfaces/VX_csr_req_inter.v
@@ -107,7 +106,6 @@ vortex_afu.json
../rtl/interfaces/VX_gpu_inst_req_inter.v ../rtl/interfaces/VX_gpu_inst_req_inter.v
../rtl/interfaces/VX_wstall_inter.v ../rtl/interfaces/VX_wstall_inter.v
../rtl/interfaces/VX_wb_inter.v ../rtl/interfaces/VX_wb_inter.v
../rtl/interfaces/VX_gpr_clone_inter.v
../rtl/interfaces/VX_gpr_read_inter.v ../rtl/interfaces/VX_gpr_read_inter.v
../rtl/interfaces/VX_mem_req_inter.v ../rtl/interfaces/VX_mem_req_inter.v
../rtl/interfaces/VX_jal_response_inter.v ../rtl/interfaces/VX_jal_response_inter.v

4
hw/rtl/VX_csr_data.v
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@@ -8,10 +8,10 @@ module VX_csr_data (
input wire in_write_valid, input wire in_write_valid,
input wire[`CSR_WIDTH-1:0] in_write_csr_data, input wire[`CSR_WIDTH-1:0] in_write_csr_data,
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
// We use a smaller storage for CSRs than the standard 4KB in RISC-V // We use a smaller storage for CSRs than the standard 4KB in RISC-V
input wire[`CSR_ADDR_SIZE-1:0] in_write_csr_address, input wire[`CSR_ADDR_SIZE-1:0] in_write_csr_address,
/* verilator lint_on UNUSED */ `IGNORE_WARNINGS_END
output wire[31:0] out_read_csr_data, output wire[31:0] out_read_csr_data,

6
hw/rtl/VX_define.vh
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@@ -9,6 +9,12 @@
// `define ASIC 1 // `define ASIC 1
// `define SYN_FUNC 1 // `define SYN_FUNC 1
`define DEBUG_BEGIN /* verilator lint_off UNUSED */
`define DEBUG_END /* verilator lint_on UNUSED */
`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */
`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */
`define STRINGIFY(x) `"x`" `define STRINGIFY(x) `"x`"
`define STATIC_ASSERT(cond, msg) \ `define STATIC_ASSERT(cond, msg) \

8
hw/rtl/VX_execute_unit.v
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@@ -23,9 +23,9 @@ module VX_execute_unit (
wire[4:0] in_alu_op; wire[4:0] in_alu_op;
wire in_rs2_src; wire in_rs2_src;
wire[31:0] in_itype_immed; wire[31:0] in_itype_immed;
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire[2:0] in_branch_type; wire[2:0] in_branch_type;
/* verilator lint_on UNUSED */ `DEBUG_END
wire[19:0] in_upper_immed; wire[19:0] in_upper_immed;
wire in_jal; wire in_jal;
wire[31:0] in_jal_offset; wire[31:0] in_jal_offset;
@@ -69,10 +69,10 @@ module VX_execute_unit (
assign out_delay = no_slot_exec || internal_stall; assign out_delay = no_slot_exec || internal_stall;
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire [$clog2(`NUM_THREADS)-1:0] jal_branch_use_index; wire [$clog2(`NUM_THREADS)-1:0] jal_branch_use_index;
wire jal_branch_found_valid; wire jal_branch_found_valid;
/* verilator lint_on UNUSED */ `DEBUG_END
VX_generic_priority_encoder #( VX_generic_priority_encoder #(
.N(`NUM_THREADS) .N(`NUM_THREADS)

4
hw/rtl/VX_fetch.v
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@@ -97,9 +97,9 @@ module VX_fetch (
assign fe_inst_meta_fi.valid = thread_mask; assign fe_inst_meta_fi.valid = thread_mask;
assign fe_inst_meta_fi.instruction = 32'h0; assign fe_inst_meta_fi.instruction = 32'h0;
assign fe_inst_meta_fi.inst_pc = warp_pc; assign fe_inst_meta_fi.inst_pc = warp_pc;
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0); wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0);
wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0); wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0);
/* verilator lint_on UNUSED */ `DEBUG_END
endmodule endmodule

4
hw/rtl/VX_front_end.v
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@@ -30,10 +30,6 @@ VX_inst_meta_inter fd_inst_meta_de();
wire total_freeze = schedule_delay; wire total_freeze = schedule_delay;
wire icache_stage_delay; wire icache_stage_delay;
/* verilator lint_off UNUSED */
// wire real_fetch_ebreak;
/* verilator lint_on UNUSED */
wire vortex_ebreak; wire vortex_ebreak;
wire terminate_sim; wire terminate_sim;

4
hw/rtl/VX_generic_queue_ll.v
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@@ -2,14 +2,14 @@ module VX_generic_queue_ll #(
parameter DATAW, parameter DATAW,
parameter SIZE = 16 parameter SIZE = 16
) ( ) (
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire push, input wire push,
input wire pop, input wire pop,
output wire empty, output wire empty,
output wire full, output wire full,
/* verilator lint_on UNUSED */ `IGNORE_WARNINGS_END
input wire [DATAW-1:0] in_data, input wire [DATAW-1:0] in_data,
output wire [DATAW-1:0] out_data output wire [DATAW-1:0] out_data
); );

4
hw/rtl/VX_generic_register.v
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@@ -2,12 +2,12 @@ module VX_generic_register #(
parameter N, parameter N,
parameter PassThru = 0 parameter PassThru = 0
) ( ) (
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire stall, input wire stall,
input wire flush, input wire flush,
/* verilator lint_on UNUSED */ `IGNORE_WARNINGS_END
input wire[N-1:0] in, input wire[N-1:0] in,
output wire[N-1:0] out output wire[N-1:0] out
); );

6
hw/rtl/VX_gpgpu_inst.v
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@@ -44,9 +44,9 @@ module VX_gpgpu_inst (
assign vx_warp_ctl.is_barrier = vx_gpu_inst_req.is_barrier && valid_inst; assign vx_warp_ctl.is_barrier = vx_gpu_inst_req.is_barrier && valid_inst;
assign vx_warp_ctl.barrier_id = vx_gpu_inst_req.a_reg_data[0]; assign vx_warp_ctl.barrier_id = vx_gpu_inst_req.a_reg_data[0];
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire[31:0] num_warps_m1 = vx_gpu_inst_req.rd2 - 1; wire[31:0] num_warps_m1 = vx_gpu_inst_req.rd2 - 1;
/* verilator lint_on UNUSED */ `DEBUG_END
assign vx_warp_ctl.num_warps = num_warps_m1[$clog2(`NUM_WARPS):0]; assign vx_warp_ctl.num_warps = num_warps_m1[$clog2(`NUM_WARPS):0];

8
hw/rtl/VX_gpr_stage.v
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@@ -23,13 +23,13 @@ module VX_gpr_stage (
VX_gpu_inst_req_inter vx_gpu_inst_req, VX_gpu_inst_req_inter vx_gpu_inst_req,
VX_csr_req_inter vx_csr_req VX_csr_req_inter vx_csr_req
); );
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire[31:0] curr_PC = vx_bckE_req.curr_PC; wire[31:0] curr_PC = vx_bckE_req.curr_PC;
wire[2:0] branchType = vx_bckE_req.branch_type; wire[2:0] branchType = vx_bckE_req.branch_type;
wire is_store = (vx_bckE_req.mem_write != `NO_MEM_WRITE); wire is_store = (vx_bckE_req.mem_write != `NO_MEM_WRITE);
wire is_load = (vx_bckE_req.mem_read != `NO_MEM_READ); wire is_load = (vx_bckE_req.mem_read != `NO_MEM_READ);
wire jalQual = vx_bckE_req.jalQual; wire jalQual = vx_bckE_req.jalQual;
/* verilator lint_on UNUSED */ `DEBUG_END
VX_gpr_read_inter vx_gpr_read(); VX_gpr_read_inter vx_gpr_read();
assign vx_gpr_read.rs1 = vx_bckE_req.rs1; assign vx_gpr_read.rs1 = vx_bckE_req.rs1;
@@ -76,9 +76,9 @@ module VX_gpr_stage (
.vx_gpu_inst_req (vx_gpu_inst_req_temp), .vx_gpu_inst_req (vx_gpu_inst_req_temp),
.vx_csr_req (vx_csr_req_temp) .vx_csr_req (vx_csr_req_temp)
); );
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire is_lsu = (|vx_lsu_req_temp.valid); wire is_lsu = (|vx_lsu_req_temp.valid);
/* verilator lint_on UNUSED */ `DEBUG_END
wire stall_rest = 0; wire stall_rest = 0;
wire flush_rest = schedule_delay; wire flush_rest = schedule_delay;

4
hw/rtl/VX_lsu.v
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@@ -70,9 +70,9 @@ module VX_lsu (
wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index; wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index;
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire found; wire found;
/* verilator lint_on UNUSED */ `DEBUG_END
VX_generic_priority_encoder #(.N(`NUM_THREADS)) pick_first_pc( VX_generic_priority_encoder #(.N(`NUM_THREADS)) pick_first_pc(
.valids(vx_dcache_rsp.core_wb_valid), .valids(vx_dcache_rsp.core_wb_valid),

11
hw/rtl/VX_warp_scheduler.v
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@@ -19,9 +19,9 @@ module VX_warp_scheduler (
input wire[`NW_BITS-1:0] whalt_warp_num, input wire[`NW_BITS-1:0] whalt_warp_num,
input wire is_barrier, input wire is_barrier,
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
input wire[31:0] barrier_id, input wire[31:0] barrier_id,
/* verilator lint_on UNUSED */ `DEBUG_END
input wire[$clog2(`NUM_WARPS):0] num_warps, input wire[$clog2(`NUM_WARPS):0] num_warps,
input wire[`NW_BITS-1:0] barrier_warp_num, input wire[`NW_BITS-1:0] barrier_warp_num,
@@ -71,12 +71,12 @@ module VX_warp_scheduler (
wire[31:0] join_pc; wire[31:0] join_pc;
wire[`NUM_THREADS-1:0] join_tm; wire[`NUM_THREADS-1:0] join_tm;
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire in_wspawn = wspawn; wire in_wspawn = wspawn;
wire in_ctm = ctm; wire in_ctm = ctm;
wire in_whalt = whalt; wire in_whalt = whalt;
wire in_wstall = wstall; wire in_wstall = wstall;
/* verilator lint_on UNUSED */ `DEBUG_END
reg[`NUM_WARPS-1:0] warp_active; reg[`NUM_WARPS-1:0] warp_active;
reg[`NUM_WARPS-1:0] warp_stalled; reg[`NUM_WARPS-1:0] warp_stalled;
@@ -115,9 +115,6 @@ module VX_warp_scheduler (
reg didnt_split; reg didnt_split;
// wire[$clog2(`NUM_WARPS):0] num_active;
/* verilator lint_on UNUSED */
integer curr_w_help; integer curr_w_help;
integer curr_barrier; integer curr_barrier;
always @(posedge clk) begin always @(posedge clk) begin

4
hw/rtl/Vortex.v
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@@ -89,9 +89,9 @@ module Vortex
output wire out_ebreak output wire out_ebreak
`endif `endif
); );
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire scheduler_empty; wire scheduler_empty;
/* verilator lint_on UNUSED */ `DEBUG_END
wire memory_delay; wire memory_delay;
wire exec_delay; wire exec_delay;

8
hw/rtl/generic_cache/VX_bank.v
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@@ -304,9 +304,9 @@ module VX_bank #(
wire valid_st1 [STAGE_1_CYCLES-1:0]; wire valid_st1 [STAGE_1_CYCLES-1:0];
wire is_fill_st1 [STAGE_1_CYCLES-1:0]; wire is_fill_st1 [STAGE_1_CYCLES-1:0];
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire going_to_write_st1[STAGE_1_CYCLES-1:0]; wire going_to_write_st1[STAGE_1_CYCLES-1:0];
/* verilator lint_on UNUSED */ `DEBUG_END
wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0]; wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
integer p_stage; integer p_stage;
@@ -417,12 +417,12 @@ module VX_bank #(
wire miss_st1e; wire miss_st1e;
wire dirty_st1e; wire dirty_st1e;
wire[31:0] pc_st1e; wire[31:0] pc_st1e;
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire [4:0] rd_st1e; wire [4:0] rd_st1e;
wire [1:0] wb_st1e; wire [1:0] wb_st1e;
wire [`NW_BITS-1:0] warp_num_st1e; wire [`NW_BITS-1:0] warp_num_st1e;
wire [`LOG2UP(NUM_REQUESTS)-1:0] tid_st1e; wire [`LOG2UP(NUM_REQUESTS)-1:0] tid_st1e;
/* verilator lint_on UNUSED */ `DEBUG_END
wire [2:0] mem_read_st1e; wire [2:0] mem_read_st1e;
wire [2:0] mem_write_st1e; wire [2:0] mem_write_st1e;
wire fill_saw_dirty_st1e; wire fill_saw_dirty_st1e;

4
hw/rtl/generic_cache/VX_cache.v
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@@ -115,9 +115,9 @@ module VX_cache #(
wire dfqq_full; wire dfqq_full;
wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid; wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid;
wire [NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; wire [NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp; wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp;
/* verilator lint_on UNUSED */ `DEBUG_END
wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready; wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop; wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop;

6
hw/rtl/generic_cache/VX_cache_dram_req_arb.v
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@@ -94,9 +94,11 @@ module VX_cache_dram_req_arb #(
); );
wire[31:0] dfqq_req_addr; wire[31:0] dfqq_req_addr;
/* verilator lint_off UNUSED */
`DEBUG_BEGIN
wire dfqq_empty; wire dfqq_empty;
/* verilator lint_on UNUSED */ `DEBUG_END
wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_full; // If no dwb, and dfqq has valids, then pop wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_full; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req_valid); wire dfqq_push = (|per_bank_dram_fill_req_valid);

4
hw/rtl/generic_cache/VX_cache_miss_resrv.v
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@@ -61,10 +61,10 @@ module VX_cache_miss_resrv #(
// Broadcast Fill // Broadcast Fill
input wire is_fill_st1, input wire is_fill_st1,
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
// TODO: should fix this // TODO: should fix this
input wire[31:0] fill_addr_st1, input wire[31:0] fill_addr_st1,
/* verilator lint_on UNUSED */ `IGNORE_WARNINGS_END
// Miss dequeue // Miss dequeue
input wire miss_resrv_pop, input wire miss_resrv_pop,

4
hw/rtl/generic_cache/VX_cache_req_queue.v
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@@ -103,9 +103,9 @@ module VX_cache_req_queue #(
wire [NUM_REQUESTS-1:0][2:0] qual_mem_write; wire [NUM_REQUESTS-1:0][2:0] qual_mem_write;
wire [31:0] qual_pc; wire [31:0] qual_pc;
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
reg [NUM_REQUESTS-1:0] updated_valids; reg [NUM_REQUESTS-1:0] updated_valids;
/* verilator lint_on UNUSED */ `DEBUG_END
wire o_empty; wire o_empty;

20
hw/rtl/generic_cache/VX_tag_data_access.v
View File

@@ -48,17 +48,13 @@ module VX_tag_data_access #(
input wire is_snp_st1e, input wire is_snp_st1e,
input wire stall_bank_pipe, input wire stall_bank_pipe,
// Initial Reading // Initial Reading
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
// TODO: // TODO: should fix this
input wire[31:0] readaddr_st10, input wire[31:0] readaddr_st10,
/* verilator lint_on UNUSED */ input wire[31:0] writeaddr_st1e,
// Write/Read Logic `IGNORE_WARNINGS_END
input wire valid_req_st1e, input wire valid_req_st1e,
input wire writefill_st1e, input wire writefill_st1e,
/* verilator lint_off UNUSED */
// TODO:
input wire[31:0] writeaddr_st1e,
/* verilator lint_on UNUSED */
input wire[`WORD_SIZE_RNG] writeword_st1e, input wire[`WORD_SIZE_RNG] writeword_st1e,
input wire[`DBANK_LINE_WORDS-1:0][31:0] writedata_st1e, input wire[`DBANK_LINE_WORDS-1:0][31:0] writedata_st1e,
input wire[2:0] mem_write_st1e, input wire[2:0] mem_write_st1e,
@@ -176,7 +172,7 @@ module VX_tag_data_access #(
wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG]; wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG];
wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG]; wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG];
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
wire lw = valid_req_st1e && (mem_read_st1e == `LW_MEM_READ); wire lw = valid_req_st1e && (mem_read_st1e == `LW_MEM_READ);
wire lb = valid_req_st1e && (mem_read_st1e == `LB_MEM_READ); wire lb = valid_req_st1e && (mem_read_st1e == `LB_MEM_READ);
wire lh = valid_req_st1e && (mem_read_st1e == `LH_MEM_READ); wire lh = valid_req_st1e && (mem_read_st1e == `LH_MEM_READ);
@@ -187,14 +183,14 @@ module VX_tag_data_access #(
wire b1 = (byte_select == 1); wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2); wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3); wire b3 = (byte_select == 3);
/* verilator lint_on UNUSED */ `IGNORE_WARNINGS_END
/* verilator lint_off UNUSED */ `DEBUG_BEGIN
wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0]; wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0];
wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0]; wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0];
wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0]; wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0];
wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0]; wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0];
/* verilator lint_on UNUSED */ `DEBUG_END
/////////////////////// STORE LOGIC /////////////////// /////////////////////// STORE LOGIC ///////////////////

4
hw/rtl/interfaces/VX_exec_unit_req_inter.v
View File

@@ -33,10 +33,10 @@ interface VX_exec_unit_req_inter ();
wire jal; wire jal;
wire [31:0] jal_offset; wire [31:0] jal_offset;
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
wire ebreak; wire ebreak;
wire wspawn; wire wspawn;
/* verilator lint_on UNUSED */ `IGNORE_WARNINGS_END
// CSR info // CSR info
wire is_csr; wire is_csr;

4
hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v
View File

@@ -21,9 +21,9 @@ interface VX_frE_to_bckE_req_inter ();
wire [2:0] branch_type; wire [2:0] branch_type;
wire [19:0] upper_immed; wire [19:0] upper_immed;
wire [31:0] curr_PC; wire [31:0] curr_PC;
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
wire ebreak; wire ebreak;
/* verilator lint_on UNUSED */ `IGNORE_WARNINGS_END
wire jalQual; wire jalQual;
wire jal; wire jal;
wire [31:0] jal_offset; wire [31:0] jal_offset;

14
hw/rtl/interfaces/VX_gpr_clone_inter.v
View File

@@ -1,14 +0,0 @@
`ifndef VX_GPR_CLONE_INTER
`define VX_GPR_CLONE_INTER
`include "../VX_define.vh"
interface VX_gpr_clone_inter ();
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_BITS-1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface
`endif

14
hw/rtl/interfaces/VX_gpr_wspawn_inter.v
View File

@@ -1,14 +0,0 @@
`ifndef VX_GPR_WSPAWN_INTER
`define VX_GPR_WSPAWN_INTER
`include "../VX_define.vh"
interface VX_gpr_wspawn_inter ();
/* verilator lint_off UNUSED */
wire is_wspawn;
wire [`NW_BITS-1:0] which_wspawn;
// wire[`NW_BITS-1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface
`endif

4
hw/rtl/interfaces/VX_gpu_dcache_rsp_inter.v
View File

@@ -9,10 +9,10 @@ interface VX_gpu_dcache_rsp_inter #(
// Cache WB // Cache WB
wire [NUM_REQUESTS-1:0] core_wb_valid; wire [NUM_REQUESTS-1:0] core_wb_valid;
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
wire [4:0] core_wb_req_rd; wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb; wire [1:0] core_wb_req_wb;
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_END
wire [`NW_BITS-1:0] core_wb_warp_num; wire [`NW_BITS-1:0] core_wb_warp_num;
wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata; wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata;
wire [NUM_REQUESTS-1:0][31:0] core_wb_pc; wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;

4
hw/rtl/interfaces/VX_warp_ctl_inter.v
View File

@@ -23,9 +23,9 @@ interface VX_warp_ctl_inter ();
wire is_split; wire is_split;
wire dont_split; wire dont_split;
/* verilator lint_off UNUSED */ `IGNORE_WARNINGS_BEGIN
wire [`NW_BITS-1:0] split_warp_num; wire [`NW_BITS-1:0] split_warp_num;
/* verilator lint_on UNUSED */ `IGNORE_WARNINGS_END
wire [`NUM_THREADS-1:0] split_new_mask; wire [`NUM_THREADS-1:0] split_new_mask;
wire [`NUM_THREADS-1:0] split_later_mask; wire [`NUM_THREADS-1:0] split_later_mask;
wire [31:0] split_save_pc; wire [31:0] split_save_pc;

4
hw/syn/synopsys/esyn.tcl
View File

@@ -4,9 +4,9 @@ set link_library [concat ./NanGate_15nm_OCL.db]
set symbol_library {} set symbol_library {}
set target_library [concat ./NanGate_15nm_OCL.db] set target_library [concat ./NanGate_15nm_OCL.db]
set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_config.vh VX_user_config.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \ set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_config.vh VX_user_config.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \
] ]
# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ # set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \
# ] # ]
set top_level Vortex set top_level Vortex

4
hw/syn/synopsys/fsyn.tcl
View File

@@ -2,9 +2,9 @@ set search_path [concat ../../models/memory/cln28hpm/rf2_128x128_wm1 ../../mod
set link_library [concat NanGate_15nm_OCL.db] set link_library [concat NanGate_15nm_OCL.db]
set symbol_library {} set symbol_library {}
set target_library [concat NanGate_15nm_OCL.db] set target_library [concat NanGate_15nm_OCL.db]
set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_bank_valid.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v rf2_128x128_wm1.v \ set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_bank_valid.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v rf2_128x128_wm1.v \
] ]
# set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \ # set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \
# ] # ]
set top_level Vortex set top_level Vortex

4
hw/syn/synopsys/syn.tcl
View File

@@ -3,9 +3,9 @@ set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_
set symbol_library {} set symbol_library {}
set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db] set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db]
set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \ set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \
] ]
# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ # set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \
# ] # ]
set top_level Vortex set top_level Vortex