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master merge fixes

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This commit is contained in:
Blaise Tine
2021-04-04 21:12:12 -07:00
parent c23c0fbe4c f8638602ef
commit 87888a9a93
27 changed files with 399 additions and 281 deletions
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3
hw/rtl/cache/VX_cache.v vendored
View File

@@ -168,8 +168,7 @@ module VX_cache #(
.NUM_BANKS (NUM_BANKS)
) flush_ctrl (
.clk (clk),
.reset (reset),
.flush (flush),
.reset (reset || flush),
.addr_out (flush_addr),
.valid_out (flush_enable)
);

6
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -98,7 +98,8 @@ module VX_cache_core_rsp_merge #(
wire core_rsp_valid_any = (| per_bank_core_rsp_valid);
VX_skid_buffer #(
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH))
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)),
.BUFFERED (1)
) pipe_reg (
.clk (clk),
.reset (reset),
@@ -146,7 +147,8 @@ module VX_cache_core_rsp_merge #(
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH)
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH),
.BUFFERED (1)
) pipe_reg (
.clk (clk),
.reset (reset),

5
hw/rtl/cache/VX_flush_ctrl.v vendored
View File

@@ -9,8 +9,7 @@ module VX_flush_ctrl #(
parameter NUM_BANKS = 1
) (
input wire clk,
input wire reset,
input wire flush,
input wire reset,
output wire [`LINE_SELECT_BITS-1:0] addr_out,
output wire valid_out
);
@@ -18,7 +17,7 @@ module VX_flush_ctrl #(
reg [`LINE_SELECT_BITS-1:0] flush_ctr;
always @(posedge clk) begin
if (reset || flush) begin
if (reset) begin
flush_enable <= 1;
flush_ctr <= 0;
end else begin