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lkg build rollout with 16cores optimization on arria10

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This commit is contained in:
Blaise Tine
2021-01-24 16:49:22 -08:00
parent 74a687e395
commit 8775f63ec4
55 changed files with 1021 additions and 868 deletions
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8
hw/rtl/libs/VX_shift_register.v
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@@ -12,7 +12,7 @@ module VX_shift_register_nr #(
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
reg [DATAW-1:0] entries [DEPTH-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] entries [DEPTH-1:0];
always @(posedge clk) begin
if (enable) begin
@@ -23,7 +23,7 @@ module VX_shift_register_nr #(
end
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out [i*DATAW+:DATAW] = entries [ TAPS[i*DEPTHW+:DEPTHW] ];
assign data_out [i*DATAW+:DATAW] = entries [TAPS[i*DEPTHW+:DEPTHW]];
end
endmodule
@@ -41,7 +41,7 @@ module VX_shift_register_wr #(
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
reg [DEPTH-1:0][DATAW-1:0] entries;
`USE_FAST_BRAM reg [DEPTH-1:0][DATAW-1:0] entries;
if (1 == DEPTH) begin
@@ -69,7 +69,7 @@ module VX_shift_register_wr #(
end
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out [i*DATAW+:DATAW] = entries [ TAPS[i*DEPTHW+:DEPTHW] ];
assign data_out [i*DATAW+:DATAW] = entries [TAPS[i*DEPTHW+:DEPTHW]];
end
endmodule