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lkg build rollout with 16cores optimization on arria10

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This commit is contained in:
Blaise Tine
2021-01-24 16:49:22 -08:00
parent 74a687e395
commit 8775f63ec4
55 changed files with 1021 additions and 868 deletions
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25
hw/rtl/fp_cores/VX_fp_cvt.v
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@@ -140,6 +140,7 @@ module VX_fp_cvt #(
wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] destination_exp; // re-biased exponent for destination
for (genvar i = 0; i < LANES; ++i) begin
`IGNORE_WARNINGS_BEGIN
// Input mantissa needs to be normalized
wire signed [INT_EXP_WIDTH-1:0] fp_input_exp;
wire signed [INT_EXP_WIDTH-1:0] int_input_exp;
@@ -153,17 +154,17 @@ module VX_fp_cvt #(
// Unbias exponent and compensate for shift
assign fp_input_exp = $signed(fmt_exponent_s0[i] +
INT_EXP_WIDTH'($signed({1'b0, in_a_type_s0[i].is_subnormal})) -
INT_EXP_WIDTH'($signed(EXP_BIAS)) -
INT_EXP_WIDTH'(renorm_shamt_sgn) +
INT_EXP_WIDTH'($signed(FMT_SHIFT_COMPENSATION)));
(($signed({1'b0, in_a_type_s0[i].is_subnormal}) +
$signed(FMT_SHIFT_COMPENSATION - EXP_BIAS)) -
renorm_shamt_sgn));
assign int_input_exp = $signed(INT_EXP_WIDTH'(INT_MAN_WIDTH - 1) - INT_EXP_WIDTH'(renorm_shamt_sgn));
assign int_input_exp = $signed(INT_MAN_WIDTH - 1 - renorm_shamt_sgn);
assign input_exp[i] = is_itof_s0 ? int_input_exp : fp_input_exp;
// Rebias the exponent
assign destination_exp[i] = input_exp[i] + INT_EXP_WIDTH'($signed(EXP_BIAS));
assign destination_exp[i] = input_exp[i] + $signed(EXP_BIAS);
`IGNORE_WARNINGS_END
end
// Pipeline stage1
@@ -207,6 +208,7 @@ module VX_fp_cvt #(
// Perform adjustments to mantissa and exponent
for (genvar i = 0; i < LANES; ++i) begin
always @(*) begin
`IGNORE_WARNINGS_BEGIN
// Default assignment
final_exp[i] = $unsigned(destination_exp_s1[i]); // take exponent as is, only look at lower bits
preshift_mant[i] = 65'b0; // initialize mantissa container with zeroes
@@ -221,16 +223,16 @@ module VX_fp_cvt #(
// Overflow or infinities (for proper rounding)
if ((destination_exp_s1[i] >= 2**EXP_BITS-1)
|| (~is_itof_s1 && in_a_type_s1[i].is_inf)) begin
final_exp[i] = INT_EXP_WIDTH'(2**EXP_BITS-2); // largest normal value
final_exp[i] = (2**EXP_BITS-2); // largest normal value
preshift_mant[i] = ~0; // largest normal value and RS bits set
of_before_round[i] = 1'b1;
// Denormalize underflowing values
end else if ((destination_exp_s1[i] < 1)
&& (destination_exp_s1[i] >= INT_EXP_WIDTH'(-$signed(MAN_BITS)))) begin
&& (destination_exp_s1[i] >= -$signed(MAN_BITS))) begin
final_exp[i] = 0; // denormal result
denorm_shamt[i] = $unsigned(denorm_shamt[i] + SHAMT_BITS'(INT_EXP_WIDTH'(1) - destination_exp_s1[i])); // adjust right shifting
denorm_shamt[i] = $unsigned(denorm_shamt[i] + 1 - destination_exp_s1[i]); // adjust right shifting
// Limit the shift to retain sticky bits
end else if (destination_exp_s1[i] < INT_EXP_WIDTH'(-$signed(MAN_BITS))) begin
end else if (destination_exp_s1[i] < -$signed(MAN_BITS)) begin
final_exp[i] = 0; // denormal result
denorm_shamt[i] = $unsigned(denorm_shamt[i] + SHAMT_BITS'(2 + MAN_BITS)); // to sticky
end
@@ -238,7 +240,7 @@ module VX_fp_cvt #(
// By default right shift mantissa to be an integer
denorm_shamt[i] = SHAMT_BITS'(MAX_INT_WIDTH-1) - SHAMT_BITS'(input_exp_s1[i]);
// overflow: when converting to unsigned the range is larger by one
if (input_exp_s1[i] >= $signed(INT_EXP_WIDTH'(MAX_INT_WIDTH-1) + INT_EXP_WIDTH'(unsigned_s1))) begin
if (input_exp_s1[i] >= $signed(MAX_INT_WIDTH -1 + unsigned_s1)) begin
denorm_shamt[i] = SHAMT_BITS'(1'b0); // prevent shifting
of_before_round[i] = 1'b1;
// underflow
@@ -246,6 +248,7 @@ module VX_fp_cvt #(
denorm_shamt[i] = MAX_INT_WIDTH + 1; // all bits go to the sticky
end
end
`IGNORE_WARNINGS_END
end
// Mantissa adjustment shift

5
hw/rtl/fp_cores/VX_fp_div.v
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@@ -29,14 +29,13 @@ module VX_fp_div #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
wire _reset;
wire _reset;
VX_reset_relay reset_relay (
.clk (clk),
.reset (reset),
.reset_out (_reset)
);
for (genvar i = 0; i < LANES; i++) begin
`ifdef VERILATOR
reg [31:0] r;

3
hw/rtl/fp_cores/VX_fp_sqrt.v
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@@ -28,8 +28,7 @@ module VX_fp_sqrt #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
wire _reset;
wire _reset;
VX_reset_relay reset_relay (
.clk (clk),
.reset (reset),