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lkg build rollout with 16cores optimization on arria10

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This commit is contained in:
Blaise Tine
2021-01-24 16:49:22 -08:00
parent 74a687e395
commit 8775f63ec4
55 changed files with 1021 additions and 868 deletions
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155
hw/rtl/cache/VX_miss_resrv.v vendored
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@@ -38,6 +38,7 @@ module VX_miss_resrv #(
input wire [`MSHR_DATA_WIDTH-1:0] enqueue_data,
input wire enqueue_is_mshr,
input wire enqueue_as_ready,
output wire enqueue_full,
output wire enqueue_almfull,
// lookup
@@ -50,9 +51,6 @@ module VX_miss_resrv #(
output wire schedule_valid,
output wire [`LINE_ADDR_WIDTH-1:0] schedule_addr,
output wire [`MSHR_DATA_WIDTH-1:0] schedule_data,
output wire schedule_valid_next,
output wire [`LINE_ADDR_WIDTH-1:0] schedule_addr_next,
output wire [`MSHR_DATA_WIDTH-1:0] schedule_data_next,
// dequeue
input wire dequeue
@@ -63,16 +61,10 @@ module VX_miss_resrv #(
reg [MSHR_SIZE-1:0] valid_table;
reg [MSHR_SIZE-1:0] ready_table;
reg [ADDRW-1:0] schedule_ptr, schedule_n_ptr;
reg [ADDRW-1:0] restore_ptr;
reg [ADDRW-1:0] head_ptr, tail_ptr;
reg [ADDRW-1:0] head_ptr, tail_ptr;
reg [ADDRW-1:0] schedule_ptr, restore_ptr;
reg [ADDRW-1:0] used_r;
reg full_r, almost_full_r;
reg schedule_valid_r, schedule_valid_n_r;
reg [`LINE_ADDR_WIDTH-1:0] schedule_addr_r, schedule_addr_n_r;
reg [`MSHR_DATA_WIDTH-1:0] dout_r, dout_n_r;
wire [`MSHR_DATA_WIDTH-1:0] dout;
reg alm_full_r, full_r;
wire [MSHR_SIZE-1:0] valid_address_match;
for (genvar i = 0; i < MSHR_SIZE; i++) begin
@@ -82,22 +74,22 @@ module VX_miss_resrv #(
assign lookup_match = (| valid_address_match);
wire push_new = enqueue && !enqueue_is_mshr;
wire restore = enqueue && enqueue_is_mshr;
wire [ADDRW-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
wire [`LOG2UP(MSHR_SIZE)-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
always @(posedge clk) begin
if (reset) begin
valid_table <= 0;
ready_table <= 0;
schedule_ptr <= 0;
schedule_n_ptr <= 1;
restore_ptr <= 0;
head_ptr <= 0;
tail_ptr <= 0;
used_r <= 0;
full_r <= 0;
almost_full_r <= 0;
valid_table <= 0;
ready_table <= 0;
head_ptr <= 0;
tail_ptr <= 0;
schedule_ptr <= 0;
restore_ptr <= 0;
used_r <= 0;
alm_full_r <= 0;
full_r <= 0;
end else begin
// WARNING: lookup should happen enqueue for ready_table's correct update
@@ -106,52 +98,46 @@ module VX_miss_resrv #(
ready_table <= ready_table | valid_address_match;
end
if (enqueue) begin
if (enqueue_is_mshr) begin
// restore schedule, returning missed msrq entry
valid_table[restore_ptr] <= 1;
ready_table[restore_ptr] <= enqueue_as_ready;
restore_ptr <= restore_ptr + $bits(restore_ptr)'(1);
schedule_ptr <= head_ptr;
schedule_n_ptr <= head_ptr_n;
end else begin
// push new entry
assert(!full_r);
valid_table[tail_ptr] <= 1;
ready_table[tail_ptr] <= enqueue_as_ready;
tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
end
if (push_new) begin
// push new entry
assert(!full_r);
valid_table[tail_ptr] <= 1;
ready_table[tail_ptr] <= enqueue_as_ready;
tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
end else if (restore) begin
assert(!schedule);
// restore schedule, returning missed mshr entry
valid_table[restore_ptr] <= 1;
ready_table[restore_ptr] <= enqueue_as_ready;
restore_ptr <= restore_ptr + $bits(restore_ptr)'(1);
schedule_ptr <= head_ptr;
end else if (dequeue) begin
// remove scheduled entry from buffer
// clear scheduled entry
assert(((head_ptr+$bits(head_ptr)'(1)) == schedule_ptr)
|| ((head_ptr+$bits(head_ptr)'(2)) == schedule_ptr)) else $error("schedule_ptr=%0d, head_ptr=%0d", schedule_ptr, head_ptr);
valid_table[head_ptr] <= 0;
head_ptr <= head_ptr_n;
restore_ptr <= head_ptr_n;
valid_table[head_ptr] <= 0;
end
if (schedule) begin
// schedule next entry
assert(schedule_valid_r);
valid_table[schedule_ptr] <= 0;
ready_table[schedule_ptr] <= 0;
schedule_ptr <= schedule_n_ptr;
if (MSHR_SIZE > 2) begin
schedule_n_ptr <= schedule_ptr + $bits(schedule_ptr)'(2);
end else begin // (MSHR_SIZE == 2);
schedule_n_ptr <= ~schedule_n_ptr;
end
// schedule next entry
assert(schedule_valid);
valid_table[schedule_ptr] <= 0;
ready_table[schedule_ptr] <= 0;
schedule_ptr <= schedule_ptr + $bits(schedule_ptr)'(1);
end
if (push_new) begin
if (!dequeue) begin
if (used_r == ADDRW'(ALM_FULL-1))
alm_full_r <= 1;
if (used_r == ADDRW'(MSHR_SIZE-1))
full_r <= 1;
if (used_r == ADDRW'(ALM_FULL-1))
almost_full_r <= 1;
end
end else if (dequeue) begin
if (used_r == ADDRW'(ALM_FULL))
almost_full_r <= 0;
alm_full_r <= 0;
full_r <= 0;
end
@@ -173,72 +159,33 @@ module VX_miss_resrv #(
) entries (
.clk(clk),
.waddr(tail_ptr),
.raddr(schedule_n_ptr),
.raddr(schedule_ptr),
.wren(push_new),
.byteen(1'b1),
.rden(1'b1),
.din(enqueue_data),
.dout(dout)
.dout(schedule_data)
);
always @(*) begin
schedule_valid_n_r = schedule_valid_r;
if (reset) begin
schedule_valid_n_r = 0;
end else begin
if (restore) begin
schedule_valid_n_r = enqueue_as_ready;
end else if (lookup_ready) begin
schedule_valid_n_r = schedule_valid_r || (schedule_addr_r == lookup_addr);
end else if (schedule) begin
schedule_valid_n_r = ready_table[schedule_n_ptr];
end
end
end
always @(*) begin
schedule_addr_n_r = schedule_addr_r;
dout_n_r = dout_r;
if (restore
|| (push_new && (used_r == 0 || (used_r == 1 && schedule)))) begin
schedule_addr_n_r = enqueue_addr;
dout_n_r = enqueue_data;
end else if (schedule) begin
schedule_addr_n_r = addr_table[schedule_n_ptr];
dout_n_r = dout;
end
end
always @(posedge clk) begin
schedule_valid_r <= schedule_valid_n_r;
schedule_addr_r <= schedule_addr_n_r;
dout_r <= dout_n_r;
end
assign schedule_valid = schedule_valid_r;
assign schedule_addr = schedule_addr_r;
assign schedule_data = dout_r;
assign schedule_valid_next = schedule_valid_n_r;
assign schedule_addr_next = schedule_addr_n_r;
assign schedule_data_next = dout_n_r;
assign enqueue_almfull = almost_full_r;
assign schedule_valid = ready_table[schedule_ptr];
assign schedule_addr = addr_table[schedule_ptr];
assign enqueue_almfull = alm_full_r;
assign enqueue_full = full_r;
`ifdef DBG_PRINT_CACHE_MSHR
always @(posedge clk) begin
if (lookup_ready || schedule || enqueue || dequeue) begin
if (schedule)
$display("%t: cache%0d:%0d msrq-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(schedule_addr, BANK_ID), deq_debug_wid, deq_debug_pc);
$display("%t: cache%0d:%0d mshr-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(schedule_addr, BANK_ID), deq_debug_wid, deq_debug_pc);
if (enqueue) begin
if (enqueue_is_mshr)
$display("%t: cache%0d:%0d msrq-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready);
$display("%t: cache%0d:%0d mshr-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready);
else
$display("%t: cache%0d:%0d msrq-enq: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready, enq_debug_wid, enq_debug_pc);
$display("%t: cache%0d:%0d mshr-enqueue: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready, enq_debug_wid, enq_debug_pc);
end
if (dequeue)
$display("%t: cache%0d:%0d msrq-deq addr%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, enq_debug_wid, enq_debug_pc);
$write("%t: cache%0d:%0d msrq-table", $time, CACHE_ID, BANK_ID);
$display("%t: cache%0d:%0d mshr-dequeue addr%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, enq_debug_wid, enq_debug_pc);
$write("%t: cache%0d:%0d mshr-table", $time, CACHE_ID, BANK_ID);
for (integer j = 0; j < MSHR_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");