benchmarks/riscv_tests Makefiles and modified testbench.cpp

benchmarks/riscv_tests/Makefile

@@ -0,0 +1,2 @@
+run:
+	$(MAKE) -C isa run

benchmarks/riscv_tests/isa/Makefile

@@ -0,0 +1,6 @@
+TESTS := $(wildcard *.hex)
+#VTESTS := $(wildcard *-v-*.hex)
+#TESTS := $(filter-out $(VTESTS) rv32ud-p-fclass.hex, $(TESTS))
+
+run:
+	cd ../../../hw/simulate/obj_dir && ./VVortex -f $(foreach test,$(TESTS),../../../benchmarks/riscv_tests/isa/$(test))

hw/simulate/testbench.cpp

@@ -143,18 +143,42 @@ int main(int argc, char **argv) {
 #endif
 
 }	else {
+	bool passed = true;
 
-	char* test = argv[2];
+	std::vector<std::string> tests(argv+2, argv+argc);
+	for (std::string test : tests) {
+		std::cerr << DEFAULT << "\n---------------------------------------\n";
+
+		std::cerr << test << std::endl;
+
+		RAM ram;
+		Simulator simulator;
+		simulator.attach_ram(&ram);
+		simulator.load_ihex(test.c_str());
+		simulator.run();
+
+		bool status = (1 == simulator.get_last_wb_value(3));
+
+		if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
+		if (!status) std::cerr << RED   << "Test Failed: " << test << std::endl;
+		std::cerr << DEFAULT;
+		passed = passed && status;
+		if (!passed)
+			break;
+	}
 	
-	std::cerr << test << std::endl;
 
-	RAM ram;
+//	char* test = argv[2];
-	Simulator simulator;
+	
-	simulator.attach_ram(&ram);
+//	std::cerr << test << std::endl;
-	simulator.load_ihex(test);
+
-	simulator.run();
+//	RAM ram;
+//	Simulator simulator;
+//	simulator.attach_ram(&ram);
+//	simulator.load_ihex(test);
+//	simulator.run();
 
 	return 0;
 }
 
-}
+}