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remove temp files

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This commit is contained in:
Blaise Tine
2020-03-01 00:30:36 -05:00
parent ef2c8f3cb9
commit 857bb54f3f
31 changed files with 19684 additions and 12542 deletions
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16
simX/obj_dir/Vcache_simX__Syms.cpp
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@@ -4,8 +4,8 @@
#include "Vcache_simX__Syms.h"
#include "Vcache_simX.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_Cache_Bank__pi9.h"
#include "Vcache_simX_VX_Cache_Bank__pi8.h"
// FUNCTIONS
@@ -22,6 +22,10 @@ Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[1].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[2].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[3].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[0].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[1].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[2].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[3].bank_structure"))
{
// Pointer to top level
TOPp = topp;
@@ -33,13 +37,21 @@ Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dcache_req.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
}