synthesizable design

2024-04-17 18:05:51 -07:00
parent 17fd29c114
commit 85213d2876
16 changed files with 110 additions and 82 deletions
--- a/hw/rtl/libs/VX_lzc.sv
+++ b/hw/rtl/libs/VX_lzc.sv
@@ -83,7 +83,7 @@ module VX_lzc_rr #(
            current_idx <= 0;
        end else begin
            if (valid_out) begin
-                current_idx = (current_idx + 1) % N;
+                current_idx <= (current_idx + 1) % N;
            end
        end
    end