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synthesizable design

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This commit is contained in:
Richard Yan
2024-04-17 18:05:51 -07:00
parent 17fd29c114
commit 85213d2876
16 changed files with 110 additions and 82 deletions
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2
hw/rtl/core/VX_lsu_unit.sv
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@@ -326,7 +326,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
`RESET_RELAY (mem_scheduler_reset, reset);
VX_mem_scheduler #(
.INSTANCE_ID ($sformatf("core%0d-lsu-memsched", CORE_ID)),
.INST_ID ($sformatf("core%0d-lsu-memsched", CORE_ID)),
.NUM_REQS (LSU_MEM_REQS),
.NUM_BANKS (DCACHE_NUM_REQS),
.ADDR_WIDTH (DCACHE_ADDR_WIDTH),

3
hw/rtl/core/VX_smem_unit.sv
View File

@@ -130,7 +130,8 @@ module VX_smem_unit import VX_gpu_pkg::*; #(
.clk (clk),
.reset (switch_reset),
.bus_in_if (dcache_bus_in_if[i]),
.bus_out_if (switch_out_bus_if[i * 2 +: 2])
.bus_out_if_0 (switch_out_bus_if[i * 2]),
.bus_out_if_1 (switch_out_bus_if[i * 2 + 1])
);
end