Added CSR TID/WID reads

This commit is contained in:
felsabbagh3
2019-10-21 02:10:05 -04:00
parent 405926f66f
commit 84f5ccb484
25 changed files with 2339 additions and 2241 deletions

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@@ -0,0 +1,24 @@
`include "../VX_define.v"
`ifndef VX_CSR_REQ
`define VX_CSR_REQ
interface VX_csr_req_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire is_csr;
wire[11:0] csr_address;
wire csr_immed;
wire[31:0] csr_mask;
endinterface
`endif

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@@ -0,0 +1,21 @@
`include "../VX_define.v"
`ifndef VX_CSR_WB_REQ
`define VX_CSR_WB_REQ
interface VX_csr_wb_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire[`NT_M1:0][31:0] csr_result;
endinterface
`endif

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@@ -1,18 +0,0 @@
`include "../VX_define.v"
`ifndef VX_CSR_W_REQ
`define VX_CSR_W_REQ
interface VX_csr_write_request_inter ();
wire is_csr;
wire[11:0] csr_address;
wire[31:0] csr_result;
endinterface
`endif

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@@ -13,6 +13,8 @@ interface VX_gpu_inst_req_inter();
wire is_split;
wire is_barrier;
wire pc_next;
wire[`NT_M1:0][31:0] a_reg_data;
wire[31:0] rd2;

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@@ -16,6 +16,13 @@ interface VX_warp_ctl_inter ();
wire ebreak;
wire is_split;
wire[`NT_M1:0] split_new_mask;
wire[`NT_M1:0] split_later_mask;
wire[31:0] split_save_pc;
endinterface