Added CSR TID/WID reads
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21
rtl/Vortex.v
21
rtl/Vortex.v
@@ -51,9 +51,7 @@ VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetc
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VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch
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// CSR Buses
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VX_csr_write_request_inter VX_csr_w_req();
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wire[31:0] csr_decode_csr_data;
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wire[11:0] decode_csr_address;
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// VX_csr_write_request_inter VX_csr_w_req();
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VX_warp_ctl_inter VX_warp_ctl();
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@@ -68,7 +66,6 @@ VX_front_end vx_front_end(
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.reset (reset),
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.VX_warp_ctl (VX_warp_ctl),
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.VX_bckE_req (VX_bckE_req),
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.decode_csr_address (decode_csr_address),
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.schedule_delay (schedule_delay),
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.icache_response_fe (icache_response_fe),
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.icache_request_fe (icache_request_fe),
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@@ -91,24 +88,22 @@ VX_back_end vx_back_end(
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.schedule_delay (schedule_delay),
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.VX_warp_ctl (VX_warp_ctl),
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.VX_bckE_req (VX_bckE_req),
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.csr_decode_csr_data (csr_decode_csr_data),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp),
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.VX_dcache_rsp (VX_dcache_rsp),
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.VX_dcache_req (VX_dcache_req),
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.VX_csr_w_req (VX_csr_w_req),
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.VX_writeback_inter (VX_writeback_inter),
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.out_mem_delay (memory_delay)
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);
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VX_csr_handler vx_csr_handler(
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.clk (clk),
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.in_decode_csr_address(decode_csr_address),
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.VX_csr_w_req (VX_csr_w_req),
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.in_wb_valid (VX_writeback_inter.wb_valid[0]),
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// VX_csr_handler vx_csr_handler(
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// .clk (clk),
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// .in_decode_csr_address(decode_csr_address),
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// .VX_csr_w_req (VX_csr_w_req),
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// .in_wb_valid (VX_writeback_inter.wb_valid[0]),
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.out_decode_csr_data (csr_decode_csr_data)
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);
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// .out_decode_csr_data (csr_decode_csr_data)
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// );
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