From 846a4036d345bdc4dd516195f04b13c3d34f40f9 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 5 Jan 2021 05:46:20 -0800 Subject: [PATCH] minor update --- hw/rtl/cache/VX_bank.v | 22 +++++++++++----------- hw/rtl/cache/VX_miss_resrv.v | 4 ++-- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index fb20ad12..ef579d0e 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -189,13 +189,13 @@ module VX_bank #( wire mshr_rw_next; wire [WORD_SIZE-1:0] mshr_byteen_next; - reg [`LINE_ADDR_WIDTH-1:0] creq_addr; + reg [`LINE_ADDR_WIDTH-1:0] creq_addr; reg [`UP(`WORD_SELECT_BITS)-1:0] creq_wsel; - reg [`REQ_TAG_WIDTH-1:0] creq_tag; - reg creq_mem_rw; - reg [WORD_SIZE-1:0] creq_byteen; - reg [`WORD_WIDTH-1:0] creq_writeword; - reg [`REQS_BITS-1:0] creq_tid; + reg [`REQ_TAG_WIDTH-1:0] creq_tag; + reg creq_mem_rw; + reg [WORD_SIZE-1:0] creq_byteen; + reg [`WORD_WIDTH-1:0] creq_writeword; + reg [`REQS_BITS-1:0] creq_tid; always @(posedge clk) begin creq_addr <= (mshr_valid_next || !drsp_empty_next) ? mshr_addr_next : creq_addr_next; @@ -405,7 +405,7 @@ end VX_pipe_register #( .DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + `CACHE_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH), .RESETW (1) - ) pipe_reg2 ( + ) pipe_reg ( .clk (clk), .reset (reset), .enable (!pipeline_stall), @@ -715,11 +715,11 @@ end if (drsq_pop) begin $display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), drsq_filldata); end - if (creq_pop) begin - if (creq_rw_st0) - $display("%t: cache%0d:%0d core-wr-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), creq_tag_st0, creq_tid_st0, creq_byteen_st0, creq_writeword_st0, debug_wid_st0, debug_pc_st0); + if (creq_pop || mshr_pop) begin + if (creq_mem_rw) + $display("%t: cache%0d:%0d core-wr-req: addr=%0h, is_mshr=%b, tag=%0h, tid=%0d, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), is_mshr_st0, creq_tag, creq_tid, creq_byteen, creq_writeword, debug_wid_st0, debug_pc_st0); else - $display("%t: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), creq_tag_st0, creq_tid_st0, creq_byteen_st0, debug_wid_st0, debug_pc_st0); + $display("%t: cache%0d:%0d core-rd-req: addr=%0h, is_mshr=%b, tag=%0h, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), is_mshr_st0, creq_tag, creq_tid, creq_byteen, debug_wid_st0, debug_pc_st0); end if (crsq_push) begin $display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag_st1, crsq_tid_st1, crsq_data_st1, debug_wid_st1, debug_pc_st1); diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v index 1d238b52..002dab64 100644 --- a/hw/rtl/cache/VX_miss_resrv.v +++ b/hw/rtl/cache/VX_miss_resrv.v @@ -206,7 +206,7 @@ module VX_miss_resrv #( assign schedule_addr_next = schedule_addr_n_r; assign schedule_data_next = dout_n_r; -/*`ifdef DBG_PRINT_CACHE_MSHR +`ifdef DBG_PRINT_CACHE_MSHR always @(posedge clk) begin if (lookup_ready || schedule || enqueue || dequeue) begin if (schedule) @@ -231,6 +231,6 @@ module VX_miss_resrv #( $write("\n"); end end -`endif*/ +`endif endmodule \ No newline at end of file