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code refactoring: DRAM => MEM renaming

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This commit is contained in:
Blaise Tine
2021-04-26 00:58:48 -07:00
parent d808aa2735
commit 8410c49f53
38 changed files with 1161 additions and 1161 deletions
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62
hw/rtl/afu/VX_avs_wrapper.v
View File

@@ -15,20 +15,20 @@ module VX_avs_wrapper #(
input wire clk,
input wire reset,
// DRAM request
input wire dram_req_valid,
input wire dram_req_rw,
input wire [AVS_BYTEENW-1:0] dram_req_byteen,
input wire [AVS_ADDRW-1:0] dram_req_addr,
input wire [AVS_DATAW-1:0] dram_req_data,
input wire [REQ_TAGW-1:0] dram_req_tag,
output wire dram_req_ready,
// Memory request
input wire mem_req_valid,
input wire mem_req_rw,
input wire [AVS_BYTEENW-1:0] mem_req_byteen,
input wire [AVS_ADDRW-1:0] mem_req_addr,
input wire [AVS_DATAW-1:0] mem_req_data,
input wire [REQ_TAGW-1:0] mem_req_tag,
output wire mem_req_ready,
// DRAM response
output wire dram_rsp_valid,
output wire [AVS_DATAW-1:0] dram_rsp_data,
output wire [REQ_TAGW-1:0] dram_rsp_tag,
input wire dram_rsp_ready,
// Memory response
output wire mem_rsp_valid,
output wire [AVS_DATAW-1:0] mem_rsp_data,
output wire [REQ_TAGW-1:0] mem_rsp_tag,
input wire mem_rsp_ready,
// AVS bus
output wire [AVS_DATAW-1:0] avs_writedata,
@@ -45,8 +45,8 @@ module VX_avs_wrapper #(
reg [AVS_BANKS_BITS-1:0] avs_bankselect_r;
reg [AVS_BURSTW-1:0] avs_burstcount_r;
wire avs_reqq_push = dram_req_valid && dram_req_ready && !dram_req_rw;
wire avs_reqq_pop = dram_rsp_valid && dram_rsp_ready;
wire avs_reqq_push = mem_req_valid && mem_req_ready && !mem_req_rw;
wire avs_reqq_pop = mem_rsp_valid && mem_rsp_ready;
wire avs_rspq_push = avs_readdatavalid;
wire avs_rspq_pop = avs_reqq_pop;
@@ -80,8 +80,8 @@ module VX_avs_wrapper #(
.reset (reset),
.push (avs_reqq_push),
.pop (avs_reqq_pop),
.data_in (dram_req_tag),
.data_out (dram_rsp_tag),
.data_in (mem_req_tag),
.data_out (mem_rsp_tag),
`UNUSED_PIN (empty),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
@@ -98,7 +98,7 @@ module VX_avs_wrapper #(
.push (avs_rspq_push),
.pop (avs_rspq_pop),
.data_in (avs_readdata),
.data_out (dram_rsp_data),
.data_out (mem_rsp_data),
.empty (avs_rspq_empty),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
@@ -106,28 +106,28 @@ module VX_avs_wrapper #(
`UNUSED_PIN (size)
);
assign avs_read = dram_req_valid && !dram_req_rw && !rsp_queue_going_full;
assign avs_write = dram_req_valid && dram_req_rw && !rsp_queue_going_full;
assign avs_address = dram_req_addr;
assign avs_byteenable = dram_req_byteen;
assign avs_writedata = dram_req_data;
assign avs_read = mem_req_valid && !mem_req_rw && !rsp_queue_going_full;
assign avs_write = mem_req_valid && mem_req_rw && !rsp_queue_going_full;
assign avs_address = mem_req_addr;
assign avs_byteenable = mem_req_byteen;
assign avs_writedata = mem_req_data;
assign avs_burstcount = avs_burstcount_r;
assign avs_bankselect = avs_bankselect_r;
assign dram_req_ready = !avs_waitrequest && !rsp_queue_going_full;
assign mem_req_ready = !avs_waitrequest && !rsp_queue_going_full;
assign dram_rsp_valid = !avs_rspq_empty;
assign mem_rsp_valid = !avs_rspq_empty;
`ifdef DBG_PRINT_AVS
always @(posedge clk) begin
if (dram_req_valid && dram_req_ready) begin
if (dram_req_rw)
$display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, dram_req_data);
if (mem_req_valid && mem_req_ready) begin
if (mem_req_rw)
$display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, mem_req_data);
else
$display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, rsp_queue_size);
$display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, rsp_queue_size);
end
if (dram_rsp_valid && dram_rsp_ready) begin
$display("%t: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d", $time, dram_rsp_tag, dram_rsp_data, rsp_queue_size);
if (mem_rsp_valid && mem_rsp_ready) begin
$display("%t: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d", $time, mem_rsp_tag, mem_rsp_data, rsp_queue_size);
end
end
`endif

106
hw/rtl/afu/VX_cci_to_mem.v
View File

@@ -11,30 +11,30 @@ module VX_cci_to_mem #(
input wire clk,
input wire reset,
input wire dram_req_valid_in,
input wire [CCI_ADDRW-1:0] dram_req_addr_in,
input wire dram_req_rw_in,
input wire [CCI_DATAW-1:0] dram_req_data_in,
input wire [TAG_WIDTH-1:0] dram_req_tag_in,
output wire dram_req_ready_in,
input wire mem_req_valid_in,
input wire [CCI_ADDRW-1:0] mem_req_addr_in,
input wire mem_req_rw_in,
input wire [CCI_DATAW-1:0] mem_req_data_in,
input wire [TAG_WIDTH-1:0] mem_req_tag_in,
output wire mem_req_ready_in,
output wire dram_req_valid_out,
output wire [AVS_ADDRW-1:0] dram_req_addr_out,
output wire dram_req_rw_out,
output wire [AVS_BYTEENW-1:0] dram_req_byteen_out,
output wire [AVS_DATAW-1:0] dram_req_data_out,
output wire [TAG_WIDTH-1:0] dram_req_tag_out,
input wire dram_req_ready_out,
output wire mem_req_valid_out,
output wire [AVS_ADDRW-1:0] mem_req_addr_out,
output wire mem_req_rw_out,
output wire [AVS_BYTEENW-1:0] mem_req_byteen_out,
output wire [AVS_DATAW-1:0] mem_req_data_out,
output wire [TAG_WIDTH-1:0] mem_req_tag_out,
input wire mem_req_ready_out,
input wire dram_rsp_valid_in,
input wire [AVS_DATAW-1:0] dram_rsp_data_in,
input wire [TAG_WIDTH-1:0] dram_rsp_tag_in,
output wire dram_rsp_ready_in,
input wire mem_rsp_valid_in,
input wire [AVS_DATAW-1:0] mem_rsp_data_in,
input wire [TAG_WIDTH-1:0] mem_rsp_tag_in,
output wire mem_rsp_ready_in,
output wire dram_rsp_valid_out,
output wire [CCI_DATAW-1:0] dram_rsp_data_out,
output wire [TAG_WIDTH-1:0] dram_rsp_tag_out,
input wire dram_rsp_ready_out
output wire mem_rsp_valid_out,
output wire [CCI_DATAW-1:0] mem_rsp_data_out,
output wire [TAG_WIDTH-1:0] mem_rsp_tag_out,
input wire mem_rsp_ready_out
);
localparam N = AVS_ADDRW - CCI_ADDRW;
@@ -44,35 +44,35 @@ module VX_cci_to_mem #(
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign dram_req_valid_out = dram_req_valid_in;
assign dram_req_addr_out = dram_req_addr_in;
assign dram_req_rw_out = dram_req_rw_in;
assign dram_req_byteen_out = {AVS_BYTEENW{1'b1}};
assign dram_req_data_out = dram_req_data_in;
assign dram_req_tag_out = dram_req_tag_in;
assign dram_req_ready_in = dram_req_ready_out;
assign mem_req_valid_out = mem_req_valid_in;
assign mem_req_addr_out = mem_req_addr_in;
assign mem_req_rw_out = mem_req_rw_in;
assign mem_req_byteen_out = {AVS_BYTEENW{1'b1}};
assign mem_req_data_out = mem_req_data_in;
assign mem_req_tag_out = mem_req_tag_in;
assign mem_req_ready_in = mem_req_ready_out;
assign dram_rsp_valid_out = dram_rsp_valid_in;
assign dram_rsp_data_out = dram_rsp_data_in;
assign dram_rsp_tag_out = dram_rsp_tag_in;
assign dram_rsp_ready_in = dram_rsp_ready_out;
assign mem_rsp_valid_out = mem_rsp_valid_in;
assign mem_rsp_data_out = mem_rsp_data_in;
assign mem_rsp_tag_out = mem_rsp_tag_in;
assign mem_rsp_ready_in = mem_rsp_ready_out;
end else begin
reg [N-1:0] req_ctr, rsp_ctr;
wire [(2**N)-1:0][AVS_DATAW-1:0] dram_req_data_w_in;
wire [(2**N)-1:0][AVS_DATAW-1:0] mem_req_data_w_in;
reg [(2**N)-1:0][AVS_DATAW-1:0] dram_rsp_data_r_out, dram_rsp_data_n_out;
reg [(2**N)-1:0][AVS_DATAW-1:0] mem_rsp_data_r_out, mem_rsp_data_n_out;
wire dram_req_fire_out = dram_req_valid_out && dram_req_ready_out;
wire dram_rsp_fire_in = dram_rsp_valid_in && dram_rsp_ready_in;
wire mem_req_fire_out = mem_req_valid_out && mem_req_ready_out;
wire mem_rsp_fire_in = mem_rsp_valid_in && mem_rsp_ready_in;
assign dram_req_data_w_in = dram_req_data_in;
assign mem_req_data_w_in = mem_req_data_in;
always @(*) begin
dram_rsp_data_n_out = dram_rsp_data_r_out;
dram_rsp_data_n_out[rsp_ctr] = dram_rsp_data_in;
mem_rsp_data_n_out = mem_rsp_data_r_out;
mem_rsp_data_n_out[rsp_ctr] = mem_rsp_data_in;
end
always @(posedge clk) begin
@@ -80,28 +80,28 @@ module VX_cci_to_mem #(
req_ctr <= 0;
rsp_ctr <= 0;
end else begin
if (dram_req_fire_out) begin
if (mem_req_fire_out) begin
req_ctr <= req_ctr + 1;
end
if (dram_rsp_fire_in) begin
if (mem_rsp_fire_in) begin
rsp_ctr <= rsp_ctr + 1;
dram_rsp_data_r_out <= dram_rsp_data_n_out;
mem_rsp_data_r_out <= mem_rsp_data_n_out;
end
end
end
assign dram_req_valid_out = dram_req_valid_in;
assign dram_req_addr_out = {dram_req_addr_in, req_ctr};
assign dram_req_rw_out = dram_req_rw_in;
assign dram_req_byteen_out = {AVS_BYTEENW{1'b1}};
assign dram_req_data_out = dram_req_data_w_in[req_ctr];
assign dram_req_tag_out = dram_req_tag_in;
assign dram_req_ready_in = dram_req_ready_out && (req_ctr == (2**N-1));
assign mem_req_valid_out = mem_req_valid_in;
assign mem_req_addr_out = {mem_req_addr_in, req_ctr};
assign mem_req_rw_out = mem_req_rw_in;
assign mem_req_byteen_out = {AVS_BYTEENW{1'b1}};
assign mem_req_data_out = mem_req_data_w_in[req_ctr];
assign mem_req_tag_out = mem_req_tag_in;
assign mem_req_ready_in = mem_req_ready_out && (req_ctr == (2**N-1));
assign dram_rsp_valid_out = dram_rsp_valid_in && (rsp_ctr == (2**N-1));
assign dram_rsp_data_out = dram_rsp_data_n_out;
assign dram_rsp_tag_out = dram_rsp_tag_in;
assign dram_rsp_ready_in = dram_rsp_ready_out;
assign mem_rsp_valid_out = mem_rsp_valid_in && (rsp_ctr == (2**N-1));
assign mem_rsp_data_out = mem_rsp_data_n_out;
assign mem_rsp_tag_out = mem_rsp_tag_in;
assign mem_rsp_ready_in = mem_rsp_ready_out;
end
endmodule

402
hw/rtl/afu/vortex_afu.sv
View File

@@ -40,19 +40,19 @@ module vortex_afu #(
localparam RESET_DELAY = 3;
localparam DRAM_LINE_WIDTH = $bits(t_local_mem_data);
localparam DRAM_ADDR_WIDTH = $bits(t_local_mem_addr);
localparam DRAM_BURST_CTRW = $bits(t_local_mem_burst_cnt);
localparam DRAM_LINE_LW = $clog2(DRAM_LINE_WIDTH);
localparam MEM_LINE_WIDTH = $bits(t_local_mem_data);
localparam MEM_ADDR_WIDTH = $bits(t_local_mem_addr);
localparam MEM_BURST_CTRW = $bits(t_local_mem_burst_cnt);
localparam MEM_LINE_LW = $clog2(MEM_LINE_WIDTH);
localparam CCI_LINE_WIDTH = $bits(t_ccip_clData);
localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_LINE_WIDTH / 8);
localparam VX_DRAM_LINE_LW = $clog2(`VX_DRAM_LINE_WIDTH);
localparam VX_DRAM_LINE_IDX = (DRAM_LINE_LW - VX_DRAM_LINE_LW);
localparam VX_MEM_LINE_LW = $clog2(`VX_MEM_LINE_WIDTH);
localparam VX_MEM_LINE_IDX = (MEM_LINE_LW - VX_MEM_LINE_LW);
localparam AVS_RD_QUEUE_SIZE = 16;
localparam AVS_REQ_TAGW = `VX_DRAM_TAG_WIDTH + VX_DRAM_LINE_IDX;
localparam AVS_REQ_TAGW = `VX_MEM_TAG_WIDTH + VX_MEM_LINE_IDX;
localparam CCI_RD_WINDOW_SIZE = 8;
localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE;
@@ -104,18 +104,18 @@ reg [STATE_WIDTH-1:0] state;
// Vortex ports ///////////////////////////////////////////////////////////////
wire vx_dram_req_valid;
wire vx_dram_req_rw;
wire [`VX_DRAM_BYTEEN_WIDTH-1:0] vx_dram_req_byteen;
wire [`VX_DRAM_ADDR_WIDTH-1:0] vx_dram_req_addr;
wire [`VX_DRAM_LINE_WIDTH-1:0] vx_dram_req_data;
wire [`VX_DRAM_TAG_WIDTH-1:0] vx_dram_req_tag;
wire vx_dram_req_ready;
wire vx_mem_req_valid;
wire vx_mem_req_rw;
wire [`VX_MEM_BYTEEN_WIDTH-1:0] vx_mem_req_byteen;
wire [`VX_MEM_ADDR_WIDTH-1:0] vx_mem_req_addr;
wire [`VX_MEM_LINE_WIDTH-1:0] vx_mem_req_data;
wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_req_tag;
wire vx_mem_req_ready;
wire vx_dram_rsp_valid;
wire [`VX_DRAM_LINE_WIDTH-1:0] vx_dram_rsp_data;
wire [`VX_DRAM_TAG_WIDTH-1:0] vx_dram_rsp_tag;
wire vx_dram_rsp_ready;
wire vx_mem_rsp_valid;
wire [`VX_MEM_LINE_WIDTH-1:0] vx_mem_rsp_data;
wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_rsp_tag;
wire vx_mem_rsp_ready;
wire vx_csr_io_req_valid;
wire [`VX_CSR_ID_WIDTH-1:0] vx_csr_io_req_coreid;
@@ -131,7 +131,7 @@ wire vx_csr_io_rsp_ready;
wire vx_busy;
reg vx_reset;
reg vx_dram_en;
reg vx_mem_en;
// CMD variables //////////////////////////////////////////////////////////////
@@ -343,7 +343,7 @@ always @(posedge clk) begin
if (reset) begin
state <= STATE_IDLE;
vx_reset <= 0;
vx_dram_en <= 0;
vx_mem_en <= 0;
end else begin
case (state)
STATE_IDLE: begin
@@ -407,14 +407,14 @@ always @(posedge clk) begin
// vortex reset cycles
if (vx_reset_ctr == $bits(vx_reset_ctr)'(RESET_DELAY)) begin
vx_reset <= 0;
vx_dram_en <= 1;
vx_mem_en <= 1;
state <= STATE_RUN;
end
end
STATE_RUN: begin
if (cmd_run_done) begin
vx_dram_en <= 0;
vx_mem_en <= 0;
state <= STATE_IDLE;
`ifdef DBG_PRINT_OPAE
$display("%t: STATE IDLE", $time);
@@ -450,164 +450,164 @@ end
// AVS Controller /////////////////////////////////////////////////////////////
wire dram_req_valid;
wire dram_req_rw;
t_local_mem_byte_mask dram_req_byteen;
t_local_mem_addr dram_req_addr;
t_local_mem_data dram_req_data;
wire [AVS_REQ_TAGW:0] dram_req_tag;
wire dram_req_ready;
wire mem_req_valid;
wire mem_req_rw;
t_local_mem_byte_mask mem_req_byteen;
t_local_mem_addr mem_req_addr;
t_local_mem_data mem_req_data;
wire [AVS_REQ_TAGW:0] mem_req_tag;
wire mem_req_ready;
wire dram_rsp_valid;
t_local_mem_data dram_rsp_data;
wire [AVS_REQ_TAGW:0] dram_rsp_tag;
wire dram_rsp_ready;
wire mem_rsp_valid;
t_local_mem_data mem_rsp_data;
wire [AVS_REQ_TAGW:0] mem_rsp_tag;
wire mem_rsp_ready;
wire cci_dram_req_tmp_valid;
wire cci_dram_req_tmp_rw;
t_local_mem_byte_mask cci_dram_req_tmp_byteen;
t_local_mem_addr cci_dram_req_tmp_addr;
t_local_mem_data cci_dram_req_tmp_data;
wire [AVS_REQ_TAGW-1:0] cci_dram_req_tmp_tag;
wire cci_dram_req_tmp_ready;
wire cci_mem_req_tmp_valid;
wire cci_mem_req_tmp_rw;
t_local_mem_byte_mask cci_mem_req_tmp_byteen;
t_local_mem_addr cci_mem_req_tmp_addr;
t_local_mem_data cci_mem_req_tmp_data;
wire [AVS_REQ_TAGW-1:0] cci_mem_req_tmp_tag;
wire cci_mem_req_tmp_ready;
wire cci_dram_rsp_tmp_valid;
t_local_mem_data cci_dram_rsp_tmp_data;
wire [AVS_REQ_TAGW-1:0] cci_dram_rsp_tmp_tag;
wire cci_dram_rsp_tmp_ready;
wire cci_mem_rsp_tmp_valid;
t_local_mem_data cci_mem_rsp_tmp_data;
wire [AVS_REQ_TAGW-1:0] cci_mem_rsp_tmp_tag;
wire cci_mem_rsp_tmp_ready;
wire vx_dram_req_valid_qual;
t_local_mem_addr vx_dram_req_addr_qual;
t_local_mem_byte_mask vx_dram_req_byteen_qual;
t_local_mem_data vx_dram_req_data_qual;
wire [AVS_REQ_TAGW-1:0] vx_dram_req_tag_qual;
wire vx_mem_req_valid_qual;
t_local_mem_addr vx_mem_req_addr_qual;
t_local_mem_byte_mask vx_mem_req_byteen_qual;
t_local_mem_data vx_mem_req_data_qual;
wire [AVS_REQ_TAGW-1:0] vx_mem_req_tag_qual;
wire [(1 << VX_DRAM_LINE_IDX)-1:0][`VX_DRAM_LINE_WIDTH-1:0] vx_dram_rsp_data_unqual;
wire [AVS_REQ_TAGW-1:0] vx_dram_rsp_tag_unqual;
wire [(1 << VX_MEM_LINE_IDX)-1:0][`VX_MEM_LINE_WIDTH-1:0] vx_mem_rsp_data_unqual;
wire [AVS_REQ_TAGW-1:0] vx_mem_rsp_tag_unqual;
wire cci_dram_rd_req_valid;
wire cci_dram_wr_req_valid;
wire [CCI_ADDR_WIDTH-1:0] cci_dram_rd_req_addr;
wire [CCI_ADDR_WIDTH-1:0] cci_dram_wr_req_addr;
wire cci_mem_rd_req_valid;
wire cci_mem_wr_req_valid;
wire [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_addr;
wire [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr;
wire [CCI_RD_RQ_DATAW-1:0] cci_rdq_dout;
wire cci_dram_req_ready;
wire cci_mem_req_ready;
wire cci_dram_rsp_valid;
wire [CCI_LINE_WIDTH-1:0] cci_dram_rsp_data;
wire [AVS_REQ_TAGW-1:0] cci_dram_rsp_tag;
wire cci_dram_rsp_ready;
wire cci_mem_rsp_valid;
wire [CCI_LINE_WIDTH-1:0] cci_mem_rsp_data;
wire [AVS_REQ_TAGW-1:0] cci_mem_rsp_tag;
wire cci_mem_rsp_ready;
//--
VX_cci_to_mem #(
.CCI_DATAW (CCI_LINE_WIDTH),
.CCI_ADDRW (CCI_ADDR_WIDTH),
.AVS_DATAW (DRAM_LINE_WIDTH),
.AVS_ADDRW (DRAM_ADDR_WIDTH),
.AVS_DATAW (MEM_LINE_WIDTH),
.AVS_ADDRW (MEM_ADDR_WIDTH),
.TAG_WIDTH (AVS_REQ_TAGW)
) cci_to_mem(
.clk (clk),
.reset (reset),
.dram_req_valid_in ((CMD_MEM_WRITE == state) ? cci_dram_wr_req_valid : cci_dram_rd_req_valid),
.dram_req_addr_in ((CMD_MEM_WRITE == state) ? cci_dram_wr_req_addr : cci_dram_rd_req_addr),
.dram_req_rw_in ((CMD_MEM_WRITE == state)),
.dram_req_data_in (cci_rdq_dout[CCI_RD_RQ_DATAW-1:CCI_RD_RQ_TAGW]),
.dram_req_tag_in (AVS_REQ_TAGW'(0)),
.dram_req_ready_in (cci_dram_req_ready),
.mem_req_valid_in ((CMD_MEM_WRITE == state) ? cci_mem_wr_req_valid : cci_mem_rd_req_valid),
.mem_req_addr_in ((CMD_MEM_WRITE == state) ? cci_mem_wr_req_addr : cci_mem_rd_req_addr),
.mem_req_rw_in ((CMD_MEM_WRITE == state)),
.mem_req_data_in (cci_rdq_dout[CCI_RD_RQ_DATAW-1:CCI_RD_RQ_TAGW]),
.mem_req_tag_in (AVS_REQ_TAGW'(0)),
.mem_req_ready_in (cci_mem_req_ready),
.dram_req_valid_out (cci_dram_req_tmp_valid),
.dram_req_addr_out (cci_dram_req_tmp_addr),
.dram_req_rw_out (cci_dram_req_tmp_rw),
.dram_req_byteen_out(cci_dram_req_tmp_byteen),
.dram_req_data_out (cci_dram_req_tmp_data),
.dram_req_tag_out (cci_dram_req_tmp_tag),
.dram_req_ready_out (cci_dram_req_tmp_ready),
.mem_req_valid_out (cci_mem_req_tmp_valid),
.mem_req_addr_out (cci_mem_req_tmp_addr),
.mem_req_rw_out (cci_mem_req_tmp_rw),
.mem_req_byteen_out(cci_mem_req_tmp_byteen),
.mem_req_data_out (cci_mem_req_tmp_data),
.mem_req_tag_out (cci_mem_req_tmp_tag),
.mem_req_ready_out (cci_mem_req_tmp_ready),
.dram_rsp_valid_in (cci_dram_rsp_tmp_valid),
.dram_rsp_data_in (cci_dram_rsp_tmp_data),
.dram_rsp_tag_in (cci_dram_rsp_tmp_tag),
.dram_rsp_ready_in (cci_dram_rsp_tmp_ready),
.mem_rsp_valid_in (cci_mem_rsp_tmp_valid),
.mem_rsp_data_in (cci_mem_rsp_tmp_data),
.mem_rsp_tag_in (cci_mem_rsp_tmp_tag),
.mem_rsp_ready_in (cci_mem_rsp_tmp_ready),
.dram_rsp_valid_out (cci_dram_rsp_valid),
.dram_rsp_data_out (cci_dram_rsp_data),
.dram_rsp_tag_out (cci_dram_rsp_tag),
.dram_rsp_ready_out (cci_dram_rsp_ready)
.mem_rsp_valid_out (cci_mem_rsp_valid),
.mem_rsp_data_out (cci_mem_rsp_data),
.mem_rsp_tag_out (cci_mem_rsp_tag),
.mem_rsp_ready_out (cci_mem_rsp_ready)
);
`UNUSED_VAR (cci_dram_rsp_tag)
`UNUSED_VAR (cci_mem_rsp_tag)
//--
assign vx_dram_req_valid_qual = vx_dram_req_valid && vx_dram_en;
assign vx_mem_req_valid_qual = vx_mem_req_valid && vx_mem_en;
assign vx_dram_req_addr_qual = vx_dram_req_addr[`VX_DRAM_ADDR_WIDTH-1:`VX_DRAM_ADDR_WIDTH-DRAM_ADDR_WIDTH];
assign vx_mem_req_addr_qual = vx_mem_req_addr[`VX_MEM_ADDR_WIDTH-1:`VX_MEM_ADDR_WIDTH-MEM_ADDR_WIDTH];
if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin
wire [VX_DRAM_LINE_IDX-1:0] vx_dram_req_idx = vx_dram_req_addr[VX_DRAM_LINE_IDX-1:0];
wire [VX_DRAM_LINE_IDX-1:0] vx_dram_rsp_idx = vx_dram_rsp_tag_unqual[VX_DRAM_LINE_IDX-1:0];
assign vx_dram_req_byteen_qual = 64'(vx_dram_req_byteen) << (6'(vx_dram_req_addr[VX_DRAM_LINE_IDX-1:0]) << (VX_DRAM_LINE_LW-3));
assign vx_dram_req_data_qual = DRAM_LINE_WIDTH'(vx_dram_req_data) << ((DRAM_LINE_LW'(vx_dram_req_idx)) << VX_DRAM_LINE_LW);
assign vx_dram_req_tag_qual = {vx_dram_req_tag, vx_dram_req_idx};
assign vx_dram_rsp_data = vx_dram_rsp_data_unqual[vx_dram_rsp_idx];
if (`VX_MEM_LINE_WIDTH != MEM_LINE_WIDTH) begin
wire [VX_MEM_LINE_IDX-1:0] vx_mem_req_idx = vx_mem_req_addr[VX_MEM_LINE_IDX-1:0];
wire [VX_MEM_LINE_IDX-1:0] vx_mem_rsp_idx = vx_mem_rsp_tag_unqual[VX_MEM_LINE_IDX-1:0];
assign vx_mem_req_byteen_qual = 64'(vx_mem_req_byteen) << (6'(vx_mem_req_addr[VX_MEM_LINE_IDX-1:0]) << (VX_MEM_LINE_LW-3));
assign vx_mem_req_data_qual = MEM_LINE_WIDTH'(vx_mem_req_data) << ((MEM_LINE_LW'(vx_mem_req_idx)) << VX_MEM_LINE_LW);
assign vx_mem_req_tag_qual = {vx_mem_req_tag, vx_mem_req_idx};
assign vx_mem_rsp_data = vx_mem_rsp_data_unqual[vx_mem_rsp_idx];
end else begin
assign vx_dram_req_byteen_qual = vx_dram_req_byteen;
assign vx_dram_req_tag_qual = vx_dram_req_tag;
assign vx_dram_req_data_qual = vx_dram_req_data;
assign vx_dram_rsp_data = vx_dram_rsp_data_unqual;
assign vx_mem_req_byteen_qual = vx_mem_req_byteen;
assign vx_mem_req_tag_qual = vx_mem_req_tag;
assign vx_mem_req_data_qual = vx_mem_req_data;
assign vx_mem_rsp_data = vx_mem_rsp_data_unqual;
end
assign vx_dram_rsp_tag = vx_dram_rsp_tag_unqual[`VX_DRAM_TAG_WIDTH+VX_DRAM_LINE_IDX-1:VX_DRAM_LINE_IDX];
assign vx_mem_rsp_tag = vx_mem_rsp_tag_unqual[`VX_MEM_TAG_WIDTH+VX_MEM_LINE_IDX-1:VX_MEM_LINE_IDX];
//--
VX_mem_arb #(
.NUM_REQS (2),
.DATA_WIDTH (DRAM_LINE_WIDTH),
.ADDR_WIDTH (DRAM_ADDR_WIDTH),
.DATA_WIDTH (MEM_LINE_WIDTH),
.ADDR_WIDTH (MEM_ADDR_WIDTH),
.TAG_IN_WIDTH (AVS_REQ_TAGW),
.TAG_OUT_WIDTH (AVS_REQ_TAGW+1)
) dram_arb (
) mem_arb (
.clk (clk),
.reset (reset),
// Source request
.req_valid_in ({cci_dram_req_tmp_valid, vx_dram_req_valid_qual}),
.req_rw_in ({cci_dram_req_tmp_rw, vx_dram_req_rw}),
.req_byteen_in ({cci_dram_req_tmp_byteen, vx_dram_req_byteen_qual}),
.req_addr_in ({cci_dram_req_tmp_addr, vx_dram_req_addr_qual}),
.req_data_in ({cci_dram_req_tmp_data, vx_dram_req_data_qual}),
.req_tag_in ({cci_dram_req_tmp_tag, vx_dram_req_tag_qual}),
.req_ready_in ({cci_dram_req_tmp_ready, vx_dram_req_ready}),
.req_valid_in ({cci_mem_req_tmp_valid, vx_mem_req_valid_qual}),
.req_rw_in ({cci_mem_req_tmp_rw, vx_mem_req_rw}),
.req_byteen_in ({cci_mem_req_tmp_byteen, vx_mem_req_byteen_qual}),
.req_addr_in ({cci_mem_req_tmp_addr, vx_mem_req_addr_qual}),
.req_data_in ({cci_mem_req_tmp_data, vx_mem_req_data_qual}),
.req_tag_in ({cci_mem_req_tmp_tag, vx_mem_req_tag_qual}),
.req_ready_in ({cci_mem_req_tmp_ready, vx_mem_req_ready}),
// DRAM request
.req_valid_out (dram_req_valid),
.req_rw_out (dram_req_rw),
.req_byteen_out (dram_req_byteen),
.req_addr_out (dram_req_addr),
.req_data_out (dram_req_data),
.req_tag_out (dram_req_tag),
.req_ready_out (dram_req_ready),
// Memory request
.req_valid_out (mem_req_valid),
.req_rw_out (mem_req_rw),
.req_byteen_out (mem_req_byteen),
.req_addr_out (mem_req_addr),
.req_data_out (mem_req_data),
.req_tag_out (mem_req_tag),
.req_ready_out (mem_req_ready),
// Source response
.rsp_valid_out ({cci_dram_rsp_tmp_valid, vx_dram_rsp_valid}),
.rsp_data_out ({cci_dram_rsp_tmp_data, vx_dram_rsp_data_unqual}),
.rsp_tag_out ({cci_dram_rsp_tmp_tag, vx_dram_rsp_tag_unqual}),
.rsp_ready_out ({cci_dram_rsp_tmp_ready, vx_dram_rsp_ready}),
.rsp_valid_out ({cci_mem_rsp_tmp_valid, vx_mem_rsp_valid}),
.rsp_data_out ({cci_mem_rsp_tmp_data, vx_mem_rsp_data_unqual}),
.rsp_tag_out ({cci_mem_rsp_tmp_tag, vx_mem_rsp_tag_unqual}),
.rsp_ready_out ({cci_mem_rsp_tmp_ready, vx_mem_rsp_ready}),
// DRAM response
.rsp_valid_in (dram_rsp_valid),
.rsp_tag_in (dram_rsp_tag),
.rsp_data_in (dram_rsp_data),
.rsp_ready_in (dram_rsp_ready)
// Memory response
.rsp_valid_in (mem_rsp_valid),
.rsp_tag_in (mem_rsp_tag),
.rsp_data_in (mem_rsp_data),
.rsp_ready_in (mem_rsp_ready)
);
//--
VX_avs_wrapper #(
.AVS_DATAW (DRAM_LINE_WIDTH),
.AVS_ADDRW (DRAM_ADDR_WIDTH),
.AVS_BURSTW (DRAM_BURST_CTRW),
.AVS_DATAW (MEM_LINE_WIDTH),
.AVS_ADDRW (MEM_ADDR_WIDTH),
.AVS_BURSTW (MEM_BURST_CTRW),
.AVS_BANKS (NUM_LOCAL_MEM_BANKS),
.REQ_TAGW (AVS_REQ_TAGW+1),
.RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE)
@@ -615,20 +615,20 @@ VX_avs_wrapper #(
.clk (clk),
.reset (reset),
// DRAM request
.dram_req_valid (dram_req_valid),
.dram_req_rw (dram_req_rw),
.dram_req_byteen (dram_req_byteen),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_tag (dram_req_tag),
.dram_req_ready (dram_req_ready),
// Memory request
.mem_req_valid (mem_req_valid),
.mem_req_rw (mem_req_rw),
.mem_req_byteen (mem_req_byteen),
.mem_req_addr (mem_req_addr),
.mem_req_data (mem_req_data),
.mem_req_tag (mem_req_tag),
.mem_req_ready (mem_req_ready),
// DRAM response
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_data (dram_rsp_data),
.dram_rsp_tag (dram_rsp_tag),
.dram_rsp_ready (dram_rsp_ready),
// Memory response
.mem_rsp_valid (mem_rsp_valid),
.mem_rsp_data (mem_rsp_data),
.mem_rsp_tag (mem_rsp_tag),
.mem_rsp_ready (mem_rsp_ready),
// AVS bus
.avs_writedata (avs_writedata),
@@ -645,10 +645,10 @@ VX_avs_wrapper #(
// CCI-P Read Request ///////////////////////////////////////////////////////////
reg [CCI_ADDR_WIDTH-1:0] cci_dram_wr_req_ctr;
reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_ctr;
reg [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr;
wire [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr_next;
reg [CCI_ADDR_WIDTH-1:0] cci_dram_wr_req_addr_unqual;
reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr_unqual;
wire [CCI_RD_RQ_TAGW-1:0] cci_rd_req_tag, cci_rd_rsp_tag;
reg [CCI_RD_RQ_TAGW-1:0] cci_rd_rsp_ctr;
t_ccip_clAddr cci_rd_req_addr;
@@ -665,7 +665,7 @@ always @(*) begin
af2cp_sTxPort.c0.hdr.mdata = t_ccip_mdata'(cci_rd_req_tag);
end
wire cci_dram_wr_req_fire = cci_dram_wr_req_valid && cci_dram_req_ready;
wire cci_mem_wr_req_fire = cci_mem_wr_req_valid && cci_mem_req_ready;
wire cci_rd_req_fire = af2cp_sTxPort.c0.valid;
@@ -678,7 +678,7 @@ assign cci_rd_rsp_tag = CCI_RD_RQ_TAGW'(cp2af_sRxPort.c0.hdr.mdata);
assign cci_rd_req_ctr_next = cci_rd_req_ctr + CCI_ADDR_WIDTH'(cci_rd_req_fire ? 1 : 0);
assign cci_rdq_pop = cci_dram_wr_req_fire;
assign cci_rdq_pop = cci_mem_wr_req_fire;
assign cci_rdq_push = cci_rd_rsp_fire;
assign cci_rdq_din = {cp2af_sRxPort.c0.data, cci_rd_rsp_tag};
@@ -697,13 +697,13 @@ VX_pending_size #(
);
`UNUSED_VAR (cci_pending_reads)
assign cci_dram_wr_req_valid = !cci_rdq_empty;
assign cci_mem_wr_req_valid = !cci_rdq_empty;
assign cci_dram_wr_req_addr = cci_dram_wr_req_addr_unqual + (CCI_ADDR_WIDTH'(CCI_RD_RQ_TAGW'(cci_rdq_dout)));
assign cci_mem_wr_req_addr = cci_mem_wr_req_addr_unqual + (CCI_ADDR_WIDTH'(CCI_RD_RQ_TAGW'(cci_rdq_dout)));
assign af2cp_sTxPort.c0.valid = cci_rd_req_enable && !(cci_rd_req_wait || cci_pending_reads_full);
assign cmd_write_done = (cci_dram_wr_req_ctr == cmd_data_size);
assign cmd_write_done = (cci_mem_wr_req_ctr == cmd_data_size);
// Send read requests to CCI
always @(posedge clk) begin
@@ -713,19 +713,19 @@ always @(posedge clk) begin
cci_rd_rsp_ctr <= 0;
cci_rd_req_enable <= 0;
cci_rd_req_wait <= 0;
cci_dram_wr_req_ctr <= 0;
cci_dram_wr_req_addr_unqual <= 0;
cci_mem_wr_req_ctr <= 0;
cci_mem_wr_req_addr_unqual <= 0;
end
else begin
if ((STATE_IDLE == state)
&& (CMD_MEM_WRITE == cmd_type)) begin
cci_rd_req_addr <= cmd_io_addr;
cci_rd_req_ctr <= 0;
cci_rd_rsp_ctr <= 0;
cci_rd_req_enable <= (cmd_data_size != 0);
cci_rd_req_wait <= 0;
cci_dram_wr_req_ctr <= 0;
cci_dram_wr_req_addr_unqual <= cmd_mem_addr;
cci_rd_req_addr <= cmd_io_addr;
cci_rd_req_ctr <= 0;
cci_rd_rsp_ctr <= 0;
cci_rd_req_enable <= (cmd_data_size != 0);
cci_rd_req_wait <= 0;
cci_mem_wr_req_ctr <= 0;
cci_mem_wr_req_addr_unqual <= cmd_mem_addr;
end
cci_rd_req_enable <= (STATE_WRITE == state)
@@ -759,9 +759,9 @@ always @(posedge clk) begin
`endif
end*/
if (cci_dram_wr_req_fire) begin
cci_dram_wr_req_addr_unqual <= cci_dram_wr_req_addr_unqual + ((CCI_RD_RQ_TAGW'(cci_dram_wr_req_ctr) == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) ? CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE) : CCI_ADDR_WIDTH'(0));
cci_dram_wr_req_ctr <= cci_dram_wr_req_ctr + CCI_ADDR_WIDTH'(1);
if (cci_mem_wr_req_fire) begin
cci_mem_wr_req_addr_unqual <= cci_mem_wr_req_addr_unqual + ((CCI_RD_RQ_TAGW'(cci_mem_wr_req_ctr) == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) ? CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE) : CCI_ADDR_WIDTH'(0));
cci_mem_wr_req_ctr <= cci_mem_wr_req_ctr + CCI_ADDR_WIDTH'(1);
end
end
end
@@ -805,22 +805,22 @@ VX_fifo_queue #(
// CCI-P Write Request //////////////////////////////////////////////////////////
reg [CCI_ADDR_WIDTH-1:0] cci_dram_rd_req_ctr;
reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_ctr;
reg [CCI_ADDR_WIDTH-1:0] cci_wr_req_ctr;
reg [CCI_ADDR_WIDTH-1:0] cci_dram_rd_req_addr_r;
reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_addr_r;
t_ccip_clAddr cci_wr_req_addr;
always @(*) begin
af2cp_sTxPort.c1.hdr = t_ccip_c1_ReqMemHdr'(0);
af2cp_sTxPort.c1.hdr.address = cci_wr_req_addr;
af2cp_sTxPort.c1.hdr.sop = 1; // single line write mode
af2cp_sTxPort.c1.data = t_ccip_clData'(cci_dram_rsp_data);
af2cp_sTxPort.c1.data = t_ccip_clData'(cci_mem_rsp_data);
end
wire cci_dram_rd_req_fire = cci_dram_rd_req_valid && cci_dram_req_ready;
wire cci_dram_rd_rsp_fire = cci_dram_rsp_valid && cci_dram_rsp_ready;
wire cci_mem_rd_req_fire = cci_mem_rd_req_valid && cci_mem_req_ready;
wire cci_mem_rd_rsp_fire = cci_mem_rsp_valid && cci_mem_rsp_ready;
wire cci_wr_req_fire = cci_dram_rd_rsp_fire;
wire cci_wr_req_fire = cci_mem_rd_rsp_fire;
wire cci_wr_rsp_fire = (STATE_READ == state)
&& cp2af_sRxPort.c1.rspValid
@@ -842,11 +842,11 @@ VX_pending_size #(
);
`UNUSED_VAR (cci_pending_writes)
assign cci_dram_rd_req_valid = (cci_dram_rd_req_ctr != 0);
assign cci_dram_rd_req_addr = cci_dram_rd_req_addr_r;
assign cci_mem_rd_req_valid = (cci_mem_rd_req_ctr != 0);
assign cci_mem_rd_req_addr = cci_mem_rd_req_addr_r;
assign af2cp_sTxPort.c1.valid = cci_dram_rd_rsp_fire;
assign cci_dram_rsp_ready = !cp2af_sRxPort.c1TxAlmFull && !cci_pending_writes_full;
assign af2cp_sTxPort.c1.valid = cci_mem_rd_rsp_fire;
assign cci_mem_rsp_ready = !cp2af_sRxPort.c1TxAlmFull && !cci_pending_writes_full;
assign cmd_read_done = (0 == cci_wr_req_ctr) && cci_pending_writes_empty;
@@ -854,18 +854,18 @@ assign cmd_read_done = (0 == cci_wr_req_ctr) && cci_pending_writes_empty;
always @(posedge clk)
begin
if (reset) begin
cci_wr_req_addr <= 0;
cci_wr_req_ctr <= 0;
cci_dram_rd_req_ctr <= 0;
cci_dram_rd_req_addr_r <= 0;
cci_wr_req_addr <= 0;
cci_wr_req_ctr <= 0;
cci_mem_rd_req_ctr <= 0;
cci_mem_rd_req_addr_r <= 0;
end
else begin
if ((STATE_IDLE == state)
&& (CMD_MEM_READ == cmd_type)) begin
cci_wr_req_addr <= cmd_io_addr;
cci_wr_req_ctr <= cmd_data_size;
cci_dram_rd_req_ctr <= cmd_data_size;
cci_dram_rd_req_addr_r <= cmd_mem_addr;
cci_wr_req_addr <= cmd_io_addr;
cci_wr_req_ctr <= cmd_data_size;
cci_mem_rd_req_ctr <= cmd_data_size;
cci_mem_rd_req_addr_r <= cmd_mem_addr;
end
if (cci_wr_req_fire) begin
@@ -883,9 +883,9 @@ begin
end
`endif*/
if (cci_dram_rd_req_fire) begin
cci_dram_rd_req_addr_r <= cci_dram_rd_req_addr_r + CCI_ADDR_WIDTH'(1);
cci_dram_rd_req_ctr <= cci_dram_rd_req_ctr - CCI_ADDR_WIDTH'(1);
if (cci_mem_rd_req_fire) begin
cci_mem_rd_req_addr_r <= cci_mem_rd_req_addr_r + CCI_ADDR_WIDTH'(1);
cci_mem_rd_req_ctr <= cci_mem_rd_req_ctr - CCI_ADDR_WIDTH'(1);
end
end
end
@@ -934,20 +934,20 @@ Vortex #() vortex (
.clk (clk),
.reset (reset | vx_reset),
// DRAM request
.dram_req_valid (vx_dram_req_valid),
.dram_req_rw (vx_dram_req_rw),
.dram_req_byteen(vx_dram_req_byteen),
.dram_req_addr (vx_dram_req_addr),
.dram_req_data (vx_dram_req_data),
.dram_req_tag (vx_dram_req_tag),
.dram_req_ready (vx_dram_req_ready),
// Memory request
.mem_req_valid (vx_mem_req_valid),
.mem_req_rw (vx_mem_req_rw),
.mem_req_byteen (vx_mem_req_byteen),
.mem_req_addr (vx_mem_req_addr),
.mem_req_data (vx_mem_req_data),
.mem_req_tag (vx_mem_req_tag),
.mem_req_ready (vx_mem_req_ready),
// DRAM response
.dram_rsp_valid (vx_dram_rsp_valid),
.dram_rsp_data (vx_dram_rsp_data),
.dram_rsp_tag (vx_dram_rsp_tag),
.dram_rsp_ready (vx_dram_rsp_ready),
// Memory response
.mem_rsp_valid (vx_mem_rsp_valid),
.mem_rsp_data (vx_mem_rsp_data),
.mem_rsp_tag (vx_mem_rsp_tag),
.mem_rsp_ready (vx_mem_rsp_ready),
// CSR Request
.csr_req_valid (vx_csr_io_req_valid),
@@ -996,8 +996,8 @@ Vortex #() vortex (
`SCOPE_ASSIGN (avs_burstcount, avs_burstcount);
`SCOPE_ASSIGN (avs_readdatavalid, avs_readdatavalid);
`SCOPE_ASSIGN (mem_bank_select, mem_bank_select);
`SCOPE_ASSIGN (cci_dram_rd_req_ctr, cci_dram_rd_req_ctr);
`SCOPE_ASSIGN (cci_dram_wr_req_ctr, cci_dram_wr_req_ctr);
`SCOPE_ASSIGN (cci_mem_rd_req_ctr, cci_mem_rd_req_ctr);
`SCOPE_ASSIGN (cci_mem_wr_req_ctr, cci_mem_wr_req_ctr);
`SCOPE_ASSIGN (cci_rd_req_ctr, cci_rd_req_ctr);
`SCOPE_ASSIGN (cci_rd_rsp_ctr, cci_rd_rsp_ctr);
`SCOPE_ASSIGN (cci_wr_req_ctr, cci_wr_req_ctr);
@@ -1008,11 +1008,11 @@ Vortex #() vortex (
`SCOPE_ASSIGN (cci_pending_reads_full, cci_pending_reads_full);
`SCOPE_ASSIGN (cci_pending_writes_empty, cci_pending_writes_empty);
`SCOPE_ASSIGN (cci_pending_writes_full, cci_pending_writes_full);
`SCOPE_ASSIGN (afu_dram_req_fire, (dram_req_valid && dram_req_ready));
`SCOPE_ASSIGN (afu_dram_req_addr, dram_req_addr);
`SCOPE_ASSIGN (afu_dram_req_tag, dram_req_tag);
`SCOPE_ASSIGN (afu_dram_rsp_fire, (dram_rsp_valid && dram_rsp_ready));
`SCOPE_ASSIGN (afu_dram_rsp_tag, dram_rsp_tag);
`SCOPE_ASSIGN (afu_mem_req_fire, (mem_req_valid && mem_req_ready));
`SCOPE_ASSIGN (afu_mem_req_addr, mem_req_addr);
`SCOPE_ASSIGN (afu_mem_req_tag, mem_req_tag);
`SCOPE_ASSIGN (afu_mem_rsp_fire, (mem_rsp_valid && mem_rsp_ready));
`SCOPE_ASSIGN (afu_mem_rsp_tag, mem_rsp_tag);
wire scope_changed = `SCOPE_TRIGGER;