Add valid / fire / cycles-issued perf counters to dispatch
This commit is contained in:
@@ -22,6 +22,9 @@ module VX_dispatch import VX_gpu_pkg::*; #(
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`ifdef PERF_ENABLE
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`ifdef PERF_ENABLE
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output wire [`PERF_CTR_BITS-1:0] perf_stalls [`NUM_EX_UNITS],
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output wire [`PERF_CTR_BITS-1:0] perf_stalls [`NUM_EX_UNITS],
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output wire [`PERF_CTR_BITS-1:0] perf_valids [`NUM_EX_UNITS],
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output wire [`PERF_CTR_BITS-1:0] perf_fires [`NUM_EX_UNITS],
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output wire [`PERF_CTR_BITS-1:0] perf_any_fire_cycles,
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`endif
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`endif
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// inputs
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// inputs
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VX_operands_if.slave operands_if [`ISSUE_WIDTH],
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VX_operands_if.slave operands_if [`ISSUE_WIDTH],
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@@ -188,6 +191,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_stalls_r;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_stalls_r;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_valids_r;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_valids_r;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_fires_r;
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reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_fires_r;
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reg [`PERF_CTR_BITS-1:0] perf_any_fire_cycles_r;
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for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
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for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
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always @(*) begin
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always @(*) begin
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@@ -232,23 +236,38 @@ module VX_dispatch import VX_gpu_pkg::*; #(
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`BUFFER(perf_unit_valids_per_cycle_r, perf_unit_valids_per_cycle);
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`BUFFER(perf_unit_valids_per_cycle_r, perf_unit_valids_per_cycle);
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`BUFFER(perf_unit_fires_per_cycle_r, perf_unit_fires_per_cycle);
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`BUFFER(perf_unit_fires_per_cycle_r, perf_unit_fires_per_cycle);
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reg perf_any_fire;
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always @(*) begin
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perf_any_fire = 1'b0;
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for (integer i = 0; i < `NUM_EX_UNITS; ++i) begin
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if (perf_unit_fires_per_cycle_r[i] != '0) begin
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perf_any_fire = 1'b1;
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end
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end
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end
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for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
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for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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perf_stalls_r[i] <= '0;
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perf_stalls_r[i] <= '0;
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perf_valids_r[i] <= '0;
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perf_valids_r[i] <= '0;
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perf_fires_r[i] <= '0;
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perf_fires_r[i] <= '0;
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perf_any_fire_cycles_r <= '0;
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end else begin
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end else begin
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perf_stalls_r[i] <= perf_stalls_r[i] + `PERF_CTR_BITS'(perf_unit_stalls_per_cycle_r[i]);
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perf_stalls_r[i] <= perf_stalls_r[i] + `PERF_CTR_BITS'(perf_unit_stalls_per_cycle_r[i]);
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perf_valids_r[i] <= perf_valids_r[i] + `PERF_CTR_BITS'(perf_unit_valids_per_cycle_r[i]);
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perf_valids_r[i] <= perf_valids_r[i] + `PERF_CTR_BITS'(perf_unit_valids_per_cycle_r[i]);
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perf_fires_r[i] <= perf_fires_r[i] + `PERF_CTR_BITS'(perf_unit_fires_per_cycle_r[i]);
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perf_fires_r[i] <= perf_fires_r[i] + `PERF_CTR_BITS'(perf_unit_fires_per_cycle_r[i]);
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perf_any_fire_cycles_r <= perf_any_fire_cycles_r + `PERF_CTR_BITS'(perf_any_fire);
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end
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end
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end
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end
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end
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end
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for (genvar i=0; i < `NUM_EX_UNITS; ++i) begin
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for (genvar i=0; i < `NUM_EX_UNITS; ++i) begin
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assign perf_stalls[i] = perf_stalls_r[i];
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assign perf_stalls[i] = perf_stalls_r[i];
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assign perf_valids[i] = perf_valids_r[i];
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assign perf_fires[i] = perf_fires_r[i];
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end
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end
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assign perf_any_fire_cycles = perf_any_fire_cycles_r;
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`endif
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`endif
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`ifdef DBG_TRACE_CORE_PIPELINE_VCS
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`ifdef DBG_TRACE_CORE_PIPELINE_VCS
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@@ -86,6 +86,10 @@ module VX_issue #(
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.reset (dispatch_reset),
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.reset (dispatch_reset),
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`ifdef PERF_ENABLE
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`ifdef PERF_ENABLE
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`UNUSED_PIN (perf_stalls),
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`UNUSED_PIN (perf_stalls),
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.perf_stalls (perf_issue_if.dispatch_stalls),
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.perf_valids (perf_issue_if.dispatch_valids),
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.perf_fires (perf_issue_if.dispatch_fires),
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.perf_any_fire_cycles (perf_issue_if.dispatch_any_fire_cycles),
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`endif
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`endif
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.operands_if (operands_if),
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.operands_if (operands_if),
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.alu_dispatch_if(alu_dispatch_if),
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.alu_dispatch_if(alu_dispatch_if),
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@@ -21,6 +21,10 @@ interface VX_pipeline_perf_if ();
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wire [`PERF_CTR_BITS-1:0] scb_stalls;
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wire [`PERF_CTR_BITS-1:0] scb_stalls;
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wire [`PERF_CTR_BITS-1:0] units_uses [`NUM_EX_UNITS];
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wire [`PERF_CTR_BITS-1:0] units_uses [`NUM_EX_UNITS];
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wire [`PERF_CTR_BITS-1:0] sfu_uses [`NUM_SFU_UNITS];
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wire [`PERF_CTR_BITS-1:0] sfu_uses [`NUM_SFU_UNITS];
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wire [`PERF_CTR_BITS-1:0] dispatch_stalls [`NUM_EX_UNITS];
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wire [`PERF_CTR_BITS-1:0] dispatch_valids [`NUM_EX_UNITS];
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wire [`PERF_CTR_BITS-1:0] dispatch_fires [`NUM_EX_UNITS];
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wire [`PERF_CTR_BITS-1:0] dispatch_any_fire_cycles;
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wire [`PERF_CTR_BITS-1:0] ifetches;
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wire [`PERF_CTR_BITS-1:0] ifetches;
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wire [`PERF_CTR_BITS-1:0] loads;
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wire [`PERF_CTR_BITS-1:0] loads;
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@@ -38,7 +42,11 @@ interface VX_pipeline_perf_if ();
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output ibf_stalls,
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output ibf_stalls,
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output scb_stalls,
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output scb_stalls,
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output units_uses,
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output units_uses,
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output sfu_uses
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output sfu_uses,
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output dispatch_stalls,
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output dispatch_valids,
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output dispatch_fires,
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output dispatch_any_fire_cycles
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);
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);
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modport slave (
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modport slave (
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@@ -49,6 +57,10 @@ interface VX_pipeline_perf_if ();
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input scb_stalls,
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input scb_stalls,
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input units_uses,
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input units_uses,
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input sfu_uses,
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input sfu_uses,
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input dispatch_stalls,
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input dispatch_valids,
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input dispatch_fires,
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input dispatch_any_fire_cycles,
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input ifetches,
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input ifetches,
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input loads,
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input loads,
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input stores,
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input stores,
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