OPAE CSR access
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@@ -288,6 +288,7 @@
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`define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH
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`define VX_SNP_TAG_WIDTH `L3SNP_TAG_WIDTH
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`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH
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`define VX_CSR_ID_WIDTH `CLOG2(`NUM_CLUSTERS * `NUM_CORES)
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`define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)}
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