minor updates
This commit is contained in:
Blaise Tine
67
hw/rtl/fp_cores/altera/acl_fp_add.v
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67
hw/rtl/fp_cores/altera/acl_fp_add.v
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// (C) 1992-2016 Intel Corporation.
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// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words
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// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.
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// and/or other countries. Other marks and brands may be claimed as the property
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// of others. See Trademarks on intel.com for full list of Intel trademarks or
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// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera)
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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module acl_fp_add(dataa, datab, clock, enable, result);
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input [31:0] dataa;
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input [31:0] datab;
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input clock, enable;
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output [31:0] result;
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// FP MAC wysiwyg
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twentynm_fp_mac mac_fp_wys (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(dataa),
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.ay(datab),
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.az(),
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.clk({2'b00,clock}),
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.ena({2'b11,enable}),
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.aclr(2'b00),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result),
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.chainout()
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);
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defparam mac_fp_wys.operation_mode = "sp_add";
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defparam mac_fp_wys.use_chainin = "false";
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defparam mac_fp_wys.adder_subtract = "false";
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defparam mac_fp_wys.ax_clock = "0";
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defparam mac_fp_wys.ay_clock = "0";
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defparam mac_fp_wys.az_clock = "none";
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defparam mac_fp_wys.output_clock = "0";
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defparam mac_fp_wys.accumulate_clock = "none";
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defparam mac_fp_wys.ax_chainin_pl_clock = "none";
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defparam mac_fp_wys.accum_pipeline_clock = "none";
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defparam mac_fp_wys.mult_pipeline_clock = "none";
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defparam mac_fp_wys.adder_input_clock = "0";
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defparam mac_fp_wys.accum_adder_clock = "none";
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endmodule
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63
hw/rtl/fp_cores/altera/acl_fp_msub.v
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63
hw/rtl/fp_cores/altera/acl_fp_msub.v
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// (C) 1992-2014 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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module acl_fp_multadd(dataa, datab, datac, clock, enable, result);
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// a*b + c
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input [31:0] dataa;
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input [31:0] datab;
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input [31:0] datac;
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input clock;
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input enable;
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output [31:0] result;
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// FP MAC wysiwyg
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twentynm_fp_mac mac_fp_wys (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(datac),
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.ay(datab),
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.az(dataa),
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.clk({2'b00,clock}),
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.ena({2'b11,enable}),
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.aclr(2'b00),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result),
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.chainout()
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);
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defparam mac_fp_wys.operation_mode = "sp_mult_add";
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defparam mac_fp_wys.use_chainin = "false";
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defparam mac_fp_wys.adder_subtract = "true";
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defparam mac_fp_wys.ax_clock = "0";
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defparam mac_fp_wys.ay_clock = "0";
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defparam mac_fp_wys.az_clock = "0";
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defparam mac_fp_wys.output_clock = "0";
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defparam mac_fp_wys.accumulate_clock = "none";
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defparam mac_fp_wys.ax_chainin_pl_clock = "0";
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defparam mac_fp_wys.accum_pipeline_clock = "none";
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defparam mac_fp_wys.mult_pipeline_clock = "0";
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defparam mac_fp_wys.adder_input_clock = "0";
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defparam mac_fp_wys.accum_adder_clock = "none";
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endmodule
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67
hw/rtl/fp_cores/altera/acl_fp_mul.v
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67
hw/rtl/fp_cores/altera/acl_fp_mul.v
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@@ -0,0 +1,67 @@
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// (C) 1992-2016 Intel Corporation.
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// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words
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// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.
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// and/or other countries. Other marks and brands may be claimed as the property
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// of others. See Trademarks on intel.com for full list of Intel trademarks or
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// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera)
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
|
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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module acl_fp_mul(dataa, datab, clock, enable, result);
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input [31:0] dataa;
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input [31:0] datab;
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input clock, enable;
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output [31:0] result;
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// FP MAC wysiwyg
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twentynm_fp_mac mac_fp_wys (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(),
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.ay(datab),
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.az(dataa),
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.clk({2'b00,clock}),
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.ena({2'b11,enable}),
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.aclr(2'b00),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result),
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.chainout()
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);
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defparam mac_fp_wys.operation_mode = "sp_mult";
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defparam mac_fp_wys.use_chainin = "false";
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defparam mac_fp_wys.adder_subtract = "false";
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defparam mac_fp_wys.ax_clock = "none";
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defparam mac_fp_wys.ay_clock = "0";
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defparam mac_fp_wys.az_clock = "0";
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defparam mac_fp_wys.output_clock = "0";
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defparam mac_fp_wys.accumulate_clock = "none";
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defparam mac_fp_wys.ax_chainin_pl_clock = "none";
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defparam mac_fp_wys.accum_pipeline_clock = "none";
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defparam mac_fp_wys.mult_pipeline_clock = "0";
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defparam mac_fp_wys.adder_input_clock = "none";
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defparam mac_fp_wys.accum_adder_clock = "none";
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endmodule
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63
hw/rtl/fp_cores/altera/acl_fp_nmadd.v
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63
hw/rtl/fp_cores/altera/acl_fp_nmadd.v
Normal file
@@ -0,0 +1,63 @@
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// (C) 1992-2014 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
|
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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module acl_fp_multadd(dataa, datab, datac, clock, enable, result);
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// a*b + c
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input [31:0] dataa;
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input [31:0] datab;
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input [31:0] datac;
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input clock;
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input enable;
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output [31:0] result;
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// FP MAC wysiwyg
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twentynm_fp_mac mac_fp_wys (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(datac),
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.ay(datab),
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.az(dataa),
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.clk({2'b00,clock}),
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.ena({2'b11,enable}),
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.aclr(2'b00),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result),
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.chainout()
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);
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defparam mac_fp_wys.operation_mode = "sp_mult_add";
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defparam mac_fp_wys.use_chainin = "false";
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defparam mac_fp_wys.adder_subtract = "false";
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defparam mac_fp_wys.ax_clock = "0";
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defparam mac_fp_wys.ay_clock = "0";
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defparam mac_fp_wys.az_clock = "0";
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defparam mac_fp_wys.output_clock = "0";
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defparam mac_fp_wys.accumulate_clock = "none";
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defparam mac_fp_wys.ax_chainin_pl_clock = "0";
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defparam mac_fp_wys.accum_pipeline_clock = "none";
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defparam mac_fp_wys.mult_pipeline_clock = "0";
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defparam mac_fp_wys.adder_input_clock = "0";
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defparam mac_fp_wys.accum_adder_clock = "none";
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endmodule
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67
hw/rtl/fp_cores/altera/acl_fp_sub.v
Normal file
67
hw/rtl/fp_cores/altera/acl_fp_sub.v
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@@ -0,0 +1,67 @@
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// (C) 1992-2016 Intel Corporation.
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// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words
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||||
// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.
|
||||
// and/or other countries. Other marks and brands may be claimed as the property
|
||||
// of others. See Trademarks on intel.com for full list of Intel trademarks or
|
||||
// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera)
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
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module acl_fp_add(dataa, datab, clock, enable, result);
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input [31:0] dataa;
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input [31:0] datab;
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input clock, enable;
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output [31:0] result;
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// FP MAC wysiwyg
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twentynm_fp_mac mac_fp_wys (
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// inputs
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.accumulate(),
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.chainin_overflow(),
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.chainin_invalid(),
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.chainin_underflow(),
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.chainin_inexact(),
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.ax(dataa),
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.ay(datab),
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.az(),
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.clk({2'b00,clock}),
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.ena({2'b11,enable}),
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.aclr(2'b00),
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.chainin(),
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// outputs
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.overflow(),
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.invalid(),
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.underflow(),
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.inexact(),
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.chainout_overflow(),
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.chainout_invalid(),
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.chainout_underflow(),
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.chainout_inexact(),
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.resulta(result),
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.chainout()
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);
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defparam mac_fp_wys.operation_mode = "sp_add";
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defparam mac_fp_wys.use_chainin = "false";
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defparam mac_fp_wys.adder_subtract = "true";
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defparam mac_fp_wys.ax_clock = "0";
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defparam mac_fp_wys.ay_clock = "0";
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defparam mac_fp_wys.az_clock = "none";
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defparam mac_fp_wys.output_clock = "0";
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defparam mac_fp_wys.accumulate_clock = "none";
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defparam mac_fp_wys.ax_chainin_pl_clock = "none";
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defparam mac_fp_wys.accum_pipeline_clock = "none";
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defparam mac_fp_wys.mult_pipeline_clock = "none";
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defparam mac_fp_wys.adder_input_clock = "0";
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defparam mac_fp_wys.accum_adder_clock = "none";
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endmodule
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